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Searched refs:b0010 (Results 1 – 25 of 44) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td395 def : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
396 def : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
397 def : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
398 def : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
411 def : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
412 def : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
417 def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
418 def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
496 def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
497 def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
[all …]
DAArch64SVEInstrInfo.td130 defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul">;
252 def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">;
281 defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
327 defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
345 defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
363 defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>;
410 …defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8Only, ZPR32ExtUXT…
432 defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31>;
445 defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31>;
462 defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td335 def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
336 def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
337 def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
338 def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;
339 def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;
340 def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;
363 def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
370 def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
389 def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>;
458 def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>;
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/external/syzkaller/pkg/report/testdata/linux/report/
D23825 7f80: 9a91fddc 80117f5c 75fd7b80 0009dd60 000b0010 000000f0 801011e4 9a910000
27 7fc0: 75fd7b80 0009dd60 000b0010 000000f0 0009dd60 00000000 00000000 00000000
D24338 7fc0: 00000018 00000001 00000005 000000f0 000b0100 000b0010 000b011c 00000573
49 7fc0: 00000018 00000001 00000005 000000f0 000b0100 000b0010 000b011c 00000573
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp129 b0010 = 0x2, enumerator
151 { true, false, false, b0010, b0010, b1101, false, NONE },
154 { true, true, true, b0010, b1000, b0001, false, NONE },
156 { true, true, true, b0010, b1000, b1111, true, FILL },
159 { true, true, true, b0010, b1000, b1111, true, COPY },
/external/llvm/test/TableGen/
DBitsInit.td42 let E{3-0} = 0b0010;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DBitsInit.td42 let E{3-0} = 0b0010;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td313 class V6_vL32b_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0010>;
332 class V6_vL32b_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0010>;
491 class V6_vL32b_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0010>;
510 class V6_vL32b_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0010>;
821 class V6_vasrwh_enc : Enc_COPROC_VX_4op_r<0b0010>;
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td274 defm : int_cond_alias<"le", 0b0010>;
301 defm : fp_cond_alias<"lg", 0b0010>;
324 defm : cp_cond_alias<"12", 0b0010>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td274 defm : int_cond_alias<"le", 0b0010>;
301 defm : fp_cond_alias<"lg", 0b0010>;
324 defm : cp_cond_alias<"12", 0b0010>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td1687 let Inst{24-21} = 0b0010;
1705 let Inst{24-21} = 0b0010;
1728 let Inst{24-21} = 0b0010;
1970 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1971 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1972 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1973 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1974 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1975 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2109 let Inst{24-21} = 0b0010;
[all …]
DARMInstrNEON.td314 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
322 : NLdSt<0,0b10,0b0010,op7_4,
734 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
772 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1207 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1216 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1630 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1666 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
3557 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3558 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
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/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td569 def ANDRdRr : FRdRr<0b0010,
588 def ORRdRr : FRdRr<0b0010,
607 def EORRdRr : FRdRr<0b0010,
702 def TSTRd : FTST<0b0010,
1049 def MOVRdRr : FRdRr<0b0010,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td603 def ANDRdRr : FRdRr<0b0010,
622 def ORRdRr : FRdRr<0b0010,
641 def EORRdRr : FRdRr<0b0010,
736 def TSTRd : FTST<0b0010,
1082 def MOVRdRr : FRdRr<0b0010,
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt288 # VLD1 multi-element type=0b0010 align=0b1x
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td1873 let Inst{24-21} = 0b0010;
1893 let Inst{24-21} = 0b0010;
1917 let Inst{24-21} = 0b0010;
2243 def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;
2244 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
2245 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
2246 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
2247 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
2248 def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>;
2382 let Inst{24-21} = 0b0010;
[all …]
DARMInstrNEON.td791 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
799 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
807 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
1255 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1293 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1843 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1852 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1860 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
2303 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2339 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td1867 let Inst{24-21} = 0b0010;
1887 let Inst{24-21} = 0b0010;
1911 let Inst{24-21} = 0b0010;
2175 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2176 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2177 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2178 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2179 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2180 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2312 let Inst{24-21} = 0b0010;
[all …]
DARMInstrNEON.td781 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
789 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
797 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
1215 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1253 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1767 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1776 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1784 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
2212 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2248 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt288 # VLD1 multi-element type=0b0010 align=0b1x
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td589 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
590 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
591 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
592 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
640 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
641 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
670 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
671 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
726 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
727 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td587 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
588 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
589 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
590 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
638 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
639 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
668 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
669 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
724 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
725 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
/external/u-boot/arch/arm/dts/
Drk322x.dtsi278 pwm1: pwm@110b0010 {
/external/skqp/include/core/
DSkCanvas.h1793 kTop_QuadAAFlag = 0b0010,

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