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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td96 def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;
352 def : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
353 def : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
378 def : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
379 def : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
405 def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
406 def : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
407 def : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
408 def : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>;
505 def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
[all …]
DAArch64SVEInstrInfo.td132 defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">;
254 def ANDS_PPzPP : sve_int_pred_log<0b0100, "ands">;
283 defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
329 defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
347 defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
365 defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>;
412 defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
421 defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
434 defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2>;
447 defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td94 def : DC<"ZVA", 0b01, 0b011, 0b0111, 0b0100, 0b001>;
247 def : TLBI<"IPAS2E1", 0b01, 0b100, 0b1000, 0b0100, 0b001>;
248 def : TLBI<"IPAS2LE1", 0b01, 0b100, 0b1000, 0b0100, 0b101>;
341 def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
342 def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;
372 def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>;
391 def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>;
418 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;
424 def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
460 def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>;
[all …]
/external/syzkaller/pkg/report/testdata/linux/report/
D24338 7fc0: 00000018 00000001 00000005 000000f0 000b0100 000b0010 000b011c 00000573
49 7fc0: 00000018 00000001 00000005 000000f0 000b0100 000b0010 000b011c 00000573
/external/swiftshader/third_party/LLVM/test/MC/AsmParser/
Ddirective_values.s26 .quad 0b0100
/external/llvm/test/MC/AsmParser/
Ddirective_values.s26 .quad 0b0100
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AsmParser/
Ddirective_values.s26 .quad 0b0100
/external/llvm/lib/Target/Hexagon/
DHexagonSystemInst.td126 let Inst{27-24} = 0b0100;
DHexagonInstrInfo.td313 let Inst{27-24} = 0b0100;
363 let Inst{27-24} = 0b0100;
526 let Inst{27-24} = 0b0100;
990 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
1696 let IClass = 0b0100;
1782 def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
1981 def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>;
2120 def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
2186 def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>;
2278 def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt462 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
467 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt462 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
467 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td278 defm : int_cond_alias<"leu", 0b0100>;
299 defm : fp_cond_alias<"l", 0b0100>;
322 defm : cp_cond_alias<"1", 0b0100>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td278 defm : int_cond_alias<"leu", 0b0100>;
299 defm : fp_cond_alias<"l", 0b0100>;
322 defm : cp_cond_alias<"1", 0b0100>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td417 let Inst{11-8} = 0b0100;
522 let Inst{11-8} = 0b0100;
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td415 let Inst{11-8} = 0b0100;
520 let Inst{11-8} = 0b0100;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td432 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
433 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
434 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
451 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
452 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
453 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
602 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
638 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1326 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1327 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
[all …]
DARMInstrThumb2.td778 let Inst{26-23} = 0b0100;
1020 let Inst{26-23} = 0b0100;
1038 let Inst{26-23} = 0b0100;
1054 let Inst{26-23} = 0b0100;
1072 let Inst{26-23} = 0b0100;
1084 let Inst{26-23} = 0b0100;
1961 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1962 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1963 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1964 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
[all …]
DARMInstrVFP.td274 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
279 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
289 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
294 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td886 let Inst{26-23} = 0b0100;
1129 let Inst{26-23} = 0b0100;
1147 let Inst{26-23} = 0b0100;
1163 let Inst{26-23} = 0b0100;
1181 let Inst{26-23} = 0b0100;
1194 let Inst{26-23} = 0b0100;
2166 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2167 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2168 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2169 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
[all …]
DARMInstrNEON.td914 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
915 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
916 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
933 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
934 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
935 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
1084 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1119 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1916 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1917 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
[all …]
DARMInstrVFP.td501 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
506 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
515 def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
522 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
527 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
536 def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td892 let Inst{26-23} = 0b0100;
1142 let Inst{26-23} = 0b0100;
1177 let Inst{26-23} = 0b0100;
2234 def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>;
2235 def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>;
2236 def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>;
2237 def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>;
2238 def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>;
2239 def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>;
2430 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
[all …]
DARMInstrNEON.td936 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
937 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
938 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
955 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
956 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
957 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
1108 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1159 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
2004 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
2005 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
[all …]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td649 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
650 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
708 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
709 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
828 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
829 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
830 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
831 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
935 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
936 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td647 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
648 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
706 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
707 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
826 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
827 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
828 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
829 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
933 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
934 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;

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