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Searched refs:b0111 (Results 1 – 25 of 42) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;
[all …]
DAArch64SVEInstrInfo.td135 defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin">;
286 defm LD1H_D_IMM : sve_mem_cld_si<0b0111, "ld1h", Z_d, ZPR64>;
332 defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
350 defm LDNF1H_D_IMM : sve_mem_cldnf_si<0b0111, "ldnf1h", Z_d, ZPR64>;
368 defm LDFF1H_D : sve_mem_cldff_ss<0b0111, "ldff1h", Z_d, ZPR64, GPR64shifted16>;
415 defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
424 defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
437 defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2>;
450 defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2>;
467 defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td314 class V6_vL32Ub_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0111>;
333 class V6_vL32Ub_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0111>;
361 class V6_vS32Ub_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0111>;
365 class V6_vS32Ub_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0111>;
492 class V6_vL32Ub_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0111>;
511 class V6_vL32Ub_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0111>;
531 class V6_vS32Ub_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0111>;
546 class V6_vS32Ub_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b0111>;
690 class V6_vS32Ub_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b0111>;
826 class V6_vasrhubrndsat_enc : Enc_COPROC_VX_4op_r<0b0111>;
DHexagonInstrInfo.td80 let IClass = 0b0111;
338 let IClass = 0b0111;
361 let IClass = 0b0111;
444 let IClass = 0b0111;
467 let IClass = 0b0111;
479 let IClass = 0b0111;
498 let IClass = 0b0111;
524 let IClass = 0b0111;
541 let IClass = 0b0111;
611 let IClass = 0b0111;
[all …]
DHexagonInstrInfoV4.td260 let IClass = 0b0111;
301 let IClass = 0b0111;
336 let IClass = 0b0111;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
490 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
1378 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
4275 let Inst{27-24} = 0b0111;
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt437 # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
442 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
Dinvalid-thumbv7.txt283 # VLD1 multi-element type=0b0111 align=0b1x
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt437 # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
442 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
Dinvalid-thumbv7.txt283 # VLD1 multi-element type=0b0111 align=0b1x
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td284 defm : int_cond_alias<"vs", 0b0111>;
296 defm : fp_cond_alias<"u", 0b0111>;
319 defm : cp_cond_alias<"3", 0b0111>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td284 defm : int_cond_alias<"vs", 0b0111>;
296 defm : fp_cond_alias<"u", 0b0111>;
319 defm : cp_cond_alias<"3", 0b0111>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td218 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
251 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
812 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
825 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
853 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
865 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1111 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1143 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1705 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1718 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
[all …]
DARMInstrThumb.td618 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
688 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
1122 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td667 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
695 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
703 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
1293 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1306 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1334 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1346 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1651 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1677 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1685 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
[all …]
DARMInstrThumb.td705 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,
748 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,
1179 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td665 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
693 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
701 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
1334 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1347 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1375 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1387 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1715 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1741 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1749 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
[all …]
DARMInstrThumb.td722 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,
765 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,
1253 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td64 class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
DMipsMSAInstrInfo.td661 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
662 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
679 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
680 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DCellSDKIntrinsics.td385 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp134 b0111 = 0x7, enumerator
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td627 def ANDIRdK : FRdK<0b0111,
1658 def CBRRdK : FRdK<0b0111,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td661 def ANDIRdK : FRdK<0b0111,
1759 def CBRRdK : FRdK<0b0111,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td659 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
660 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
677 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
678 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;

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