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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;
[all …]
DAArch64SVEInstrInfo.td136 defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd">;
257 def ORR_PPzPP : sve_int_pred_log<0b1000, "orr">;
287 defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
333 defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>;
351 defm LDNF1SH_D_IMM : sve_mem_cldnf_si<0b1000, "ldnf1sh", Z_d, ZPR64>;
369 defm LDFF1SH_D : sve_mem_cldff_ss<0b1000, "ldff1sh", Z_d, ZPR64, GPR64shifted16>;
451 defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4>;
468 defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
481 defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>;
498 defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td315 class V6_vL32b_nt_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1000>;
334 class V6_vL32b_nt_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1000>;
362 class V6_vS32b_nt_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b1000>;
366 class V6_vS32b_nt_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b1000>;
493 class V6_vL32b_nt_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1000>;
512 class V6_vL32b_nt_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1000>;
532 class V6_vS32b_nt_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b1000>;
547 class V6_vS32b_nt_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b1000>;
691 class V6_vS32b_nt_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b1000>;
827 class V6_vasrhbrndsat_enc : Enc_COPROC_VX_4op_r<0b1000>;
[all …]
DHexagonInstrInfoV5.td134 let IClass = 0b1000;
539 let IClass = 0b1000;
558 let IClass = 0b1000;
577 let IClass = 0b1000;
579 let Inst{27-24} = 0b1000;
597 let IClass = 0b1000;
677 let IClass = 0b1000;
813 let IClass = 0b1000;
842 let IClass = 0b1000;
870 let IClass = 0b1000;
DHexagonInstrInfo.td637 let Inst{27-24} = 0b1000;
1402 let IClass = 0b1000;
1416 let IClass = 0b1000;
1728 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1922 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
2013 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
2074 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2158 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2265 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2571 let Inst{27-24} = 0b1000;
[all …]
DHexagonInstrInfoV3.td209 let Inst{27-24} = 0b1000;
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td269 defm : int_cond_alias<"a", 0b1000>;
287 defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
294 defm : fp_cond_alias<"a", 0b1000>;
312 defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
317 defm : cp_cond_alias<"a", 0b1000>;
333 let EmitPriority = 0 in defm : cp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td269 defm : int_cond_alias<"a", 0b1000>;
287 defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
294 defm : fp_cond_alias<"a", 0b1000>;
312 defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
317 defm : cp_cond_alias<"a", 0b1000>;
333 let EmitPriority = 0 in defm : cp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp135 b1000 = 0x8, enumerator
147 { false, false, false, b0001, b1000, b1111, false, NONE },
148 { true, false, false, b0001, b1000, b0000, false, NONE },
154 { true, true, true, b0010, b1000, b0001, false, NONE },
156 { true, true, true, b0010, b1000, b1111, true, FILL },
159 { true, true, true, b0010, b1000, b1111, true, COPY },
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td363 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
364 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
365 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
398 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
399 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
400 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
606 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
642 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1257 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1258 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
[all …]
DARMInstrVFP.td645 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
652 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
663 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
670 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1078 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1110 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
DARMInstrThumb.td624 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
694 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
1187 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
DARMInstrThumb2.td1840 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1930 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2604 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2817 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2819 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
3332 let Inst{15-12} = 0b1000;
3592 let Inst{15-12} = 0b1000;
3608 let Inst{15-12} = 0b1000;
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td910 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
917 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
924 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
1254 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1269 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1286 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1293 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1308 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1325 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
2084 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
[all …]
DARMInstrNEON.td831 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
833 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
835 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
869 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
871 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
873 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
1088 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1123 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1818 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1820 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
[all …]
DARMInstrThumb2.td2135 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2832 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
3091 let Inst{24-21} = 0b1000;
3104 let Inst{24-21} = 0b1000;
3120 let Inst{24-21} = 0b1000;
3758 let Inst{15-12} = 0b1000;
3769 let Inst{15-12} = 0b1000;
3854 let Inst{15-12} = 0b1000;
4055 let Inst{15-12} = 0b1000;
4098 let Inst{15-12} = 0b1000;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td948 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
955 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
962 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
1307 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1323 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1341 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1352 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1368 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1386 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
2252 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins),
[all …]
DARMInstrNEON.td853 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
855 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
857 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
891 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
893 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
895 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
1112 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1163 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1906 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1908 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
[all …]
DARMInstrThumb2.td2212 def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">;
2810 def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">,
3067 let Inst{24-21} = 0b1000;
3080 let Inst{24-21} = 0b1000;
3096 let Inst{24-21} = 0b1000;
3747 let Inst{15-12} = 0b1000;
3758 let Inst{15-12} = 0b1000;
3844 let Inst{15-12} = 0b1000;
4047 let Inst{15-12} = 0b1000;
4090 let Inst{15-12} = 0b1000;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td468 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
478 def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td676 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
677 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
738 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
739 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
838 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
839 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
840 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
841 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td527 let Inst{3-0} = 0b1000;
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td525 let Inst{3-0} = 0b1000;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td674 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
675 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
736 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
737 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
836 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
837 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
838 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
839 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;

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