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Searched refs:b1001 (Results 1 – 25 of 47) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td47 def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
48 def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
317 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
318 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
375 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
396 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
434 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
472 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
488 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
504 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
[all …]
/external/llvm/test/TableGen/
DBitsInit.td44 bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
45 bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
46 bits<9> F3 = { 0, 1, 0b1001, 0, 0b0 }; // RHS doesn't have enough bits
48 bits<8> G1 = { 0, { 1, 0b1001, 0 }, 0b0 }; // ok
49 bits<8> G2 = { 0, { 1, 0b1001 }, 0, 0b0 }; // ok
50 bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DBitsInit.td44 bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
45 bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
46 bits<9> F3 = { 0, 1, 0b1001, 0, 0b0 }; // RHS doesn't have enough bits
48 bits<8> G1 = { 0, { 1, 0b1001, 0 }, 0b0 }; // ok
49 bits<8> G2 = { 0, { 1, 0b1001 }, 0, 0b0 }; // ok
50 bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td49 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
50 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
475 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
476 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
539 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
560 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
604 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
642 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
658 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
674 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
[all …]
DAArch64SVEInstrInfo.td137 defm FSCALE_ZPmZ : sve_fp_2op_p_zds<0b1001, "fscale">;
258 def ORN_PPzPP : sve_int_pred_log<0b1001, "orn">;
288 defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
334 defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
352 defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
370 defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>;
452 defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>;
469 defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
482 defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
499 defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
[all …]
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp136 b1001 = 0x9, enumerator
155 { true, true, true, b1001, b1001, b0110, false, NONE },
157 { true, true, true, b1001, b1001, b1111, true, FILL },
158 { false, true, true, b1001, b1001, b0110, true, FILL },
160 { true, true, true, b1001, b1001, b1111, true, COPY },
161 { false, true, true, b1001, b1001, b0110, true, COPY },
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td104 let Inst{15-12} = 0b1001;
229 let Inst{15-12} = 0b1001;
369 let Inst{15-12} = 0b1001;
415 let Inst{15-12} = 0b1001;
501 let Inst{31-28} = 0b1001;
520 let Inst{15-12} = 0b1001;
DAVRInstrInfo.td516 def INCRd : FRd<0b1001,
523 def DECRd : FRd<0b1001,
541 def MULRdRr : FRdRr<0b1001, 0b11,
704 def COMRd : FRd<0b1001,
722 def NEGRd : FRd<0b1001,
1564 def PUSHRr : FRd<0b1001,
1582 def POPRd : FRd<0b1001,
1647 def LSRRd : FRd<0b1001,
1659 def ASRRd : FRd<0b1001,
1686 def RORRd : FRd<0b1001,
[all …]
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td102 let Inst{15-12} = 0b1001;
227 let Inst{15-12} = 0b1001;
367 let Inst{15-12} = 0b1001;
413 let Inst{15-12} = 0b1001;
499 let Inst{31-28} = 0b1001;
518 let Inst{15-12} = 0b1001;
DAVRInstrInfo.td482 def INCRd : FRd<0b1001,
489 def DECRd : FRd<0b1001,
507 def MULRdRr : FRdRr<0b1001, 0b11,
670 def COMRd : FRd<0b1001,
688 def NEGRd : FRd<0b1001,
1465 def PUSHRr : FRd<0b1001,
1483 def POPRd : FRd<0b1001,
1548 def LSRRd : FRd<0b1001,
1560 def ASRRd : FRd<0b1001,
1587 def RORRd : FRd<0b1001,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td1153 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1172 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1286 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1325 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1423 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1463 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1487 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1508 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1553 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
1558 def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0,
[all …]
DARMInstrNEON.td891 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
893 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
895 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
897 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
899 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
901 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
1150 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1162 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1186 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1197 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
[all …]
DARMInstrFormats.td556 let Inst{7-4} = 0b1001;
819 let Inst{7-4} = 0b1001;
827 let Inst{7-4} = 0b1001;
1148 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1523 let Inst{11-8} = 0b1001; // Half precision
1871 let Inst{11-8} = 0b1001; // Half precision
1899 let Inst{11-8} = 0b1001; // Half precision
1925 let Inst{11-8} = 0b1001; // Half precision
1954 let Inst{11-8} = 0b1001; // Half precision
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td271 defm : int_cond_alias<"ne", 0b1001>;
288 defm : int_cond_alias<"nz", 0b1001>; // same as ne
303 defm : fp_cond_alias<"e", 0b1001>;
314 defm : fp_cond_alias<"z", 0b1001>; // same as e
326 defm : cp_cond_alias<"0", 0b1001>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td271 defm : int_cond_alias<"ne", 0b1001>;
288 defm : int_cond_alias<"nz", 0b1001>; // same as ne
303 defm : fp_cond_alias<"e", 0b1001>;
314 defm : fp_cond_alias<"z", 0b1001>; // same as e
326 defm : cp_cond_alias<"0", 0b1001>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td1204 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1224 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1341 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1386 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1490 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1536 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1565 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1589 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1599 def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011,
1642 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
[all …]
DARMInstrNEON.td913 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
915 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
917 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
919 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
921 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
923 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
1190 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1202 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1226 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1237 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
[all …]
DARMInstrFormats.td576 let Inst{7-4} = 0b1001;
839 let Inst{7-4} = 0b1001;
847 let Inst{7-4} = 0b1001;
1180 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1555 let Inst{11-8} = 0b1001; // Half precision
1903 let Inst{11-8} = 0b1001; // Half precision
1931 let Inst{11-8} = 0b1001; // Half precision
1957 let Inst{11-8} = 0b1001; // Half precision
1986 let Inst{11-8} = 0b1001; // Half precision
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td415 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
416 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
417 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
418 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
419 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
420 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
669 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
681 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
705 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
716 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td316 class V6_vL32b_nt_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1001>;
335 class V6_vL32b_nt_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1001>;
494 class V6_vL32b_nt_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1001>;
513 class V6_vL32b_nt_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1001>;
828 class V6_vlutvvb_enc : Enc_COPROC_VX_4op_r<0b1001>;
DHexagonInstrInfo.td1403 let Inst{27-24} = 0b1001;
1658 let IClass = 0b1001;
1729 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1768 let IClass = 0b1001;
1848 let IClass = 0b1001;
1887 let IClass = 0b1001;
1923 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1968 let IClass = 0b1001;
2001 let IClass = 0b1001;
2014 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td482 def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">;
486 def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
490 def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_program.c423 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001; in fd3_program_emit()
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt303 # VLD2 multi-element type=0b1001 align=0b11
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_program.c530 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001; in fd4_program_emit()

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