Searched refs:b1010 (Results 1 – 25 of 46) sorted by relevance
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99 def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>;100 def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;540 def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;548 def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;561 def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;588 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;643 def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>;659 def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>;675 def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>;691 def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>;[all …]
138 defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx">;259 def NOR_PPzPP : sve_int_pred_log<0b1010, "nor">;289 defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>;335 defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>;353 defm LDNF1W_IMM : sve_mem_cldnf_si<0b1010, "ldnf1w", Z_s, ZPR32>;371 defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>;416 defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;425 defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;438 defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4>;453 defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4>;[all …]
97 def : DC<"CVAC", 0b01, 0b011, 0b0111, 0b1010, 0b001>;98 def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>;376 def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;384 def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;397 def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;418 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;473 def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>;489 def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>;505 def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>;521 def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>;[all …]
464 def VMOVRS : AVConv2I<0b11100001, 0b1010,485 def VMOVSR : AVConv4I<0b11100000, 0b1010,529 def VMOVRRS : AVConv3I<0b11000101, 0b1010,578 def VMOVSRR : AVConv5I<0b11000100, 0b1010,652 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,670 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,725 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,743 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,764 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,778 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,[all …]
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),259 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),740 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {752 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {778 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {789 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {1118 : NLdSt<0,0b00,0b1010,op7_4, (outs),1150 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),1636 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {1648 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {[all …]
26 let Inst{31-28} = 0b1010;44 let Inst{31-28} = 0b1010;98 let IClass = 0b1010;
317 class V6_vL32b_nt_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1010>;336 class V6_vL32b_nt_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1010>;456 class V6_vS32b_nt_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1010>;473 class V6_vS32b_nt_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1010>;495 class V6_vL32b_nt_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1010>;514 class V6_vL32b_nt_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1010>;643 class V6_vS32b_nt_new_pred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1010>;660 class V6_vS32b_nt_new_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1010>;738 class V6_vS32b_nt_new_pred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1010>;
1733 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;1928 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;2015 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;2079 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;2164 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;2220 let IClass = 0b1010;2267 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;2874 let Inst{27-24} = 0b1010;2949 let Inst{27-24} = 0b1010;2970 let Inst{27-24} = 0b1010;[all …]
422 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;480 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;549 let Inst{27-24} = 0b1010;702 let IClass = 0b1010;738 let IClass = 0b1010;776 let IClass = 0b1010;834 let IClass = 0b1010;1282 let IClass = 0b1010;1426 let IClass = 0b1010;1466 let IClass = 0b1010;[all …]
239 let Inst{27-24} = 0b1010;
10 def c0 : C<[0b0101, 0b1010]>;
987 def VMOVRS : AVConv2I<0b11100001, 0b1010,1009 def VMOVSR : AVConv4I<0b11100000, 0b1010,1059 def VMOVRRS : AVConv3I<0b11000101, 0b1010,1128 def VMOVSRR : AVConv5I<0b11000100, 0b1010,1269 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1308 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1405 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1445 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,1480 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1501 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,[all …]
675 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),712 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),720 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),1221 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {1233 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {1259 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {1270 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {1658 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),1695 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),1703 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),[all …]
18 int e = 0'b1010; // expected-error {{digit 'b' in octal constant}}
1030 def VMOVRS : AVConv2I<0b11100001, 0b1010,1053 def VMOVSR : AVConv4I<0b11100000, 0b1010,1107 def VMOVRRS : AVConv3I<0b11000101, 0b1010,1178 def VMOVSRR : AVConv5I<0b11000100, 0b1010,1323 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1368 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1471 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1517 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,1557 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1581 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,[all …]
673 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),710 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),718 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),1261 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {1273 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {1299 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {1310 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {1722 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),1759 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),1767 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),[all …]
137 b1010 = 0xA, enumerator152 { true, true, false, b1010, b1010, b0101, false, NONE },153 { false, true, true, b1010, b1010, b1111, false, NONE },
273 defm : int_cond_alias<"g", 0b1010>;304 defm : fp_cond_alias<"ue", 0b1010>;327 defm : cp_cond_alias<"03", 0b1010>;
188 let Inst{15-12} = 0b1010;450 let Inst{15-12} = 0b1010;
278 # VLD1 multi-element, type=0b1010 align=0b11
447 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined