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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td99 def : DC<"CVAU", 0b01, 0b011, 0b0111, 0b1011, 0b001>;
377 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
385 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
398 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
410 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
411 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
412 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
413 def : ROSysReg<"ICH_ELSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
445 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
446 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td380 // Special case encoding: bits 11-8 is 0b1011.
396 let Inst{11-8} = 0b1011;
507 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
555 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
645 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
663 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
718 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
736 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
757 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
771 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td815 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
828 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
856 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
868 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1708 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1721 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1747 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1759 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
3446 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3468 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
[all …]
DARMInstrInfo.td1619 let Inst{7-4} = 0b1011;
1852 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1862 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
2178 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2298 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2433 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2440 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2574 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2588 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2741 defm STRHT : AI3strT<0b1011, "strht">;
[all …]
DARMInstrThumb.td936 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
942 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td101 def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>;
541 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
549 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
562 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
574 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
575 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
576 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
577 def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
615 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
616 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
[all …]
DAArch64SVEInstrInfo.td260 def NAND_PPzPP : sve_int_pred_log<0b1011, "nand">;
290 defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
336 defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
354 defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;
372 defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
417 defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
426 defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
439 defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4>;
454 defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4>;
471 defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td641 // Special case encoding: bits 11-8 is 0b1011.
657 let Inst{11-8} = 0b1011;
1032 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1085 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1254 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1293 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1390 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1430 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1473 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1494 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1296 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1309 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1337 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1349 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2290 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2303 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2329 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2341 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4230 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4252 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
[all …]
DARMInstrInfo.td1929 let Inst{7-4} = 0b1011;
2212 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
2222 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
2521 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2648 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2782 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2803 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2941 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2955 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3113 defm STRHT : AI3strT<0b1011, "strht">;
[all …]
DARMInstrThumb.td991 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
997 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td654 // Special case encoding: bits 11-8 is 0b1011.
671 let Inst{11-8} = 0b1011;
1079 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1134 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1307 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1352 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1455 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1501 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1549 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1573 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1337 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1350 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1378 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1390 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2381 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2394 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2420 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2432 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4321 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4343 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
[all …]
DARMInstrInfo.td2036 let Inst{7-4} = 0b1011;
2319 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
2329 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
2631 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2758 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2892 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2913 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
3051 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3065 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3223 defm STRHT : AI3strT<0b1011, "strht">;
[all …]
DARMInstrThumb.td1065 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
1071 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td275 defm : int_cond_alias<"ge", 0b1011>;
305 defm : fp_cond_alias<"ge", 0b1011>;
328 defm : cp_cond_alias<"02", 0b1011>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td275 defm : int_cond_alias<"ge", 0b1011>;
305 defm : fp_cond_alias<"ge", 0b1011>;
328 defm : cp_cond_alias<"02", 0b1011>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td384 let IClass = 0b1011;
1374 let Inst{27-24} = 0b1011;
1734 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1929 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
2016 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2080 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2165 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2268 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
3371 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3695 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
[all …]
DHexagonInstrInfoV5.td163 let Inst{27-24} = 0b1011;
599 let Inst{27-24} = 0b1011;
DHexagonInstrInfoV4.td423 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
481 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
704 let Inst{27-24} = 0b1011;
871 let Inst{27-24} = 0b1011;
1796 let Inst{27-24} = 0b1011;
DHexagonInstrEnc.td829 class V6_vshuffvdd_enc : Enc_COPROC_VX_4op_r<0b1011>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td421 let Inst{3-0} = 0b1011;
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td419 let Inst{3-0} = 0b1011;
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DCellSDKIntrinsics.td392 RRRForm<0b1011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp138 b1011 = 0xB, enumerator

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