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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td317 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
318 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
357 def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
358 def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
359 def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
360 def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
378 def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
399 def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>;
406 def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>;
407 def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td106 def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
475 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
476 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
521 def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
522 def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
523 def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
524 def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
542 def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
563 def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>;
570 def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>;
[all …]
DAArch64SVEInstrInfo.td139 defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">;
261 def ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs">;
291 defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
337 defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
355 defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
373 defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>;
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-MOVr-arm.txt8 …To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
Dinvalid-MOVs-arm.txt8 … qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrFormats.td228 let Inst{21-18} = 0b1100;
280 let Inst{21-18} = 0b1100;
332 let Inst{21-18} = 0b1100;
DMipsMSAInstrInfo.td715 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
716 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
745 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
746 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
936 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
937 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrFormats.td227 let Inst{21-18} = 0b1100;
279 let Inst{21-18} = 0b1100;
331 let Inst{21-18} = 0b1100;
DMipsMSAInstrInfo.td717 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
718 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
747 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
748 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
938 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
939 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td1475 let Inst{27-24} = 0b1100;
1738 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1934 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
2017 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2086 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2172 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2271 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2326 let Inst{27-24} = 0b1100;
3365 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3697 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
[all …]
DHexagonInstrInfoV4.td178 let IClass = 0b1100;
429 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
489 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
2006 let IClass = 0b1100;
2028 let IClass = 0b1100;
2052 let IClass = 0b1100;
2073 let IClass = 0b1100;
2339 let Inst{27-24} = 0b1100;
2583 let Inst{27-24} = 0b1100;
2707 let IClass = 0b1100;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td756 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
764 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
772 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
780 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
788 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
803 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
1430 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1445 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1463 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1494 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1362 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1383 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1406 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1415 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1425 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1434 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
4233 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4276 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4278 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4436 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
[all …]
DARMInstrThumb2.td1645 let Inst{11-8} = 0b1100;
2245 let Inst{25-22} = 0b1100;
2256 let Inst{25-22} = 0b1100;
2892 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2900 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
3311 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3392 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
4175 let Inst{27-24} = 0b1100;
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt177 … qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
195 …To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt177 … qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
195 …To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td277 defm : int_cond_alias<"gu", 0b1100>;
306 defm : fp_cond_alias<"uge", 0b1100>;
329 defm : cp_cond_alias<"023", 0b1100>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td277 defm : int_cond_alias<"gu", 0b1100>;
306 defm : fp_cond_alias<"uge", 0b1100>;
329 defm : cp_cond_alias<"023", 0b1100>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td783 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
791 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
799 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
807 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
815 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
830 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
1501 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1517 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1536 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1573 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1403 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1425 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1448 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1457 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1467 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1476 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
4324 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4367 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4369 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4527 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
[all …]
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lschl.cfg182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td736 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
743 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
771 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
778 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
DARMInstrThumb2.td1490 let Inst{11-8} = 0b1100;
2040 let Inst{25-22} = 0b1100;
2051 let Inst{25-22} = 0b1100;
2664 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2672 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
3646 let Inst{27-24} = 0b1100;
/external/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td158 let Opcode = 0b1100;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td158 let Opcode = 0b1100;

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