Searched refs:b1101 (Results 1 – 25 of 40) sorted by relevance
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543 def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;550 def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;564 def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;646 def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>;662 def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>;678 def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>;694 def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>;773 def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;774 def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;775 def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;[all …]
140 defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">;262 def ORNS_PPzPP : sve_int_pred_log<0b1101, "orns">;292 defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;338 defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;356 defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;374 defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>;
379 def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;386 def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;400 def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;476 def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>;492 def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>;508 def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>;524 def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>;603 def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;604 def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;605 def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;[all …]
100 let Inst{12-9} = 0b1101;342 let Inst{12-9} = 0b1101;416 let Inst{12-9} = 0b1101;554 let Inst{12-9} = 0b1101;616 let Inst{12-9} = 0b1101;
54 let Inst{27-24} = 0b1101;123 let IClass = 0b1101;
227 let IClass = 0b1101;228 let Inst{27-24} = 0b1101;778 let Inst{27-24} =0b1101;1286 let Inst{24-21} = 0b1101;1882 let IClass = 0b1101;1904 let IClass = 0b1101;1926 let IClass = 0b1101;1970 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;2109 let IClass = 0b1101;2127 let IClass = 0b1101;[all …]
249 let IClass = 0b1101;261 let IClass = 0b1101;897 let IClass = 0b1101;914 let IClass = 0b1101;
802 let Inst{31-16} = { opc{7-5}, 0b1101, opc{4}, 0, opc{3-2}, src3{4-0} };831 class V6_vlutvvb_oracc_enc : Enc_COPROC_VX_4op_r<0b1101>;
866 let IClass = 0b1101;970 let IClass = 0b1101;1056 let IClass = 0b1101;1137 let IClass = 0b1101;1153 let IClass = 0b1101;1225 let IClass = 0b1101;1257 let IClass = 0b1101;1278 let IClass = 0b1101;2656 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;2660 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;[all …]
71 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),75 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),85 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),89 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),718 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,725 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,757 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,764 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
950 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),973 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),3368 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",3370 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",3417 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",3419 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",3471 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,3500 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,3510 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",3513 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",[all …]
2078 let Inst{19-16} = 0b1101; // SP2187 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,2193 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),2300 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;2302 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2316 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2432 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;2851 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,2868 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,2879 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),[all …]
279 defm : int_cond_alias<"cc", 0b1101>;291 defm : int_cond_alias<"geu", 0b1101>; // same as cc307 defm : fp_cond_alias<"le", 0b1101>;330 defm : cp_cond_alias<"01", 0b1101>;
697 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.714 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.750 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.803 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.878 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1453 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1472 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1496 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),1531 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,1536 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.[all …]
121 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),125 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),133 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),140 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),144 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),152 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),1455 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1471 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1490 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1549 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,[all …]
445 let Inst{6-3} = 0b1101;631 let Inst{15-12} = 0b1101;1204 T1DataProcessing<0b1101> {1378 let Inst{15-12} = 0b1101;
2494 let Inst{19-16} = 0b1101; // SP2640 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,2646 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),2760 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;2762 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2775 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2891 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;3360 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,3374 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,3385 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),[all …]
699 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.716 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.752 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.793 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.856 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1411 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1430 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1454 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),1482 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,1487 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.[all …]
101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),1390 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1405 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1423 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1473 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,[all …]
428 let Inst{6-3} = 0b1101;614 let Inst{15-12} = 0b1101;1130 T1DataProcessing<0b1101> {1257 let Inst{15-12} = 0b1101;
2384 let Inst{19-16} = 0b1101; // SP2530 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,2536 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),2650 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;2652 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2665 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2781 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;3250 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,3264 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,3275 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),[all …]
423 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001; in fd3_program_emit()
140 b1101 = 0xD, enumerator151 { true, false, false, b0010, b0010, b1101, false, NONE },
530 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001; in fd4_program_emit()