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Searched refs:b1111 (Results 1 – 25 of 54) sorted by relevance

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/external/clang/test/Modules/Inputs/PR27513/
Dmodule.modulemap6 module "b1111.h" { header "b1111.h" export *}
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td769 let Inst{19-16} = 0b1111; // Rn
780 let Inst{15-12} = 0b1111;
832 let Inst{11-8} = 0b1111; // Rd
844 let Inst{11-8} = 0b1111; // Rd
857 let Inst{11-8} = 0b1111; // Rd
944 let Inst{19-16} = 0b1111; // Rn
1022 let Inst{19-16} = 0b1111; // Rn
1023 let Inst{15-12} = 0b1111;
1040 let Inst{19-16} = 0b1111; // Rn
1041 let Inst{15-12} = 0b1111;
[all …]
DARMInstrNEON.td221 let Rm = 0b1111;
229 let Rm = 0b1111;
287 let Rm = 0b1111;
317 let Rm = 0b1111;
349 let Rm = 0b1111;
358 let Rm = 0b1111;
427 let Rm = 0b1111;
486 let Rm = 0b1111;
578 let Rm = 0b1111;
590 let Rm = 0b1111;
[all …]
DARMInstrInfo.td1186 let Inst{19-16} = 0b1111;
1197 let Inst{19-16} = 0b1111;
1620 let Inst{11-8} = 0b1111;
1651 let Inst{31-28} = 0b1111;
1687 let Inst{15-12} = 0b1111;
1702 let Inst{15-12} = 0b1111;
1791 let Inst{19-16} = 0b1111;
2062 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2073 let Inst{31-28} = 0b1111;
2113 let Inst{31-28} = 0b1111;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td876 let Inst{19-16} = 0b1111; // Rn
888 let Inst{15-12} = 0b1111;
934 let Inst{11-8} = 0b1111; // Rd
946 let Inst{11-8} = 0b1111; // Rd
960 let Inst{11-8} = 0b1111; // Rd
1048 let Inst{19-16} = 0b1111; // Rn
1131 let Inst{19-16} = 0b1111; // Rn
1132 let Inst{15-12} = 0b1111;
1149 let Inst{19-16} = 0b1111; // Rn
1150 let Inst{15-12} = 0b1111;
[all …]
DARMInstrInfo.td1474 let Unpredictable{15-12} = 0b1111;
1491 let Unpredictable{15-12} = 0b1111;
1508 let Unpredictable{15-12} = 0b1111;
1527 let Unpredictable{15-12} = 0b1111;
1544 let Inst{19-16} = 0b1111;
1555 let Inst{19-16} = 0b1111;
1930 let Inst{11-8} = 0b1111;
1931 let Unpredictable{11-8} = 0b1111;
1968 let Inst{31-28} = 0b1111;
2005 let Inst{15-12} = 0b1111;
[all …]
DARMInstrNEON.td670 let Rm = 0b1111;
678 let Rm = 0b1111;
743 let Rm = 0b1111;
784 let Rm = 0b1111;
826 let Rm = 0b1111;
909 let Rm = 0b1111;
968 let Rm = 0b1111;
1060 let Rm = 0b1111;
1072 let Rm = 0b1111;
1139 let Rm = 0b1111;
[all …]
DARMInstrFormats.td599 let Unpredictable{11-8} = 0b1111;
612 let Inst{15-12} = 0b1111;
918 let Inst{19-16} = 0b1111;
920 let Inst{11-8} = 0b1111;
936 let Inst{15-12} = 0b1111;
1638 let Inst{31-28} = 0b1111;
1694 let Inst{31-28} = 0b1111;
1748 let Inst{31-28} = 0b1111;
1811 let Inst{31-28} = 0b1111;
1888 let Inst{31-28} = 0b1111;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td882 let Inst{19-16} = 0b1111; // Rn
894 let Inst{15-12} = 0b1111;
940 let Inst{11-8} = 0b1111; // Rd
952 let Inst{11-8} = 0b1111; // Rd
966 let Inst{11-8} = 0b1111; // Rd
1058 let Inst{19-16} = 0b1111; // Rn
1144 let Inst{19-16} = 0b1111; // Rn
1145 let Inst{15-12} = 0b1111;
1179 let Inst{15-12} = 0b1111;
1215 let Inst{19-16} = 0b1111; // Rn
[all …]
DARMInstrInfo.td1578 let Unpredictable{15-12} = 0b1111;
1595 let Unpredictable{15-12} = 0b1111;
1612 let Unpredictable{15-12} = 0b1111;
1631 let Unpredictable{15-12} = 0b1111;
1648 let Inst{19-16} = 0b1111;
1659 let Inst{19-16} = 0b1111;
2037 let Inst{11-8} = 0b1111;
2038 let Unpredictable{11-8} = 0b1111;
2075 let Inst{31-28} = 0b1111;
2112 let Inst{15-12} = 0b1111;
[all …]
DARMInstrNEON.td668 let Rm = 0b1111;
676 let Rm = 0b1111;
741 let Rm = 0b1111;
794 let Rm = 0b1111;
848 let Rm = 0b1111;
931 let Rm = 0b1111;
991 let Rm = 0b1111;
1083 let Rm = 0b1111;
1095 let Rm = 0b1111;
1179 let Rm = 0b1111;
[all …]
DARMInstrFormats.td619 let Unpredictable{11-8} = 0b1111;
632 let Inst{15-12} = 0b1111;
938 let Inst{19-16} = 0b1111;
940 let Inst{11-8} = 0b1111;
956 let Inst{15-12} = 0b1111;
1670 let Inst{31-28} = 0b1111;
1726 let Inst{31-28} = 0b1111;
1780 let Inst{31-28} = 0b1111;
1843 let Inst{31-28} = 0b1111;
1920 let Inst{31-28} = 0b1111;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td545 def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
552 def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
566 def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
648 def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
664 def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
680 def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
696 def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
845 def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
870 def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
871 def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
[all …]
DAArch64SVEInstrInfo.td264 def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">;
294 defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>;
340 defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
358 defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>;
376 defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>;
456 defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8>;
473 defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
486 defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>;
503 defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
516 defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
[all …]
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp142 b1111 = 0xF, enumerator
147 { false, false, false, b0001, b1000, b1111, false, NONE },
150 { true, false, false, b1111, b1111, b0000, false, NONE },
153 { false, true, true, b1010, b1010, b1111, false, NONE },
156 { true, true, true, b0010, b1000, b1111, true, FILL },
157 { true, true, true, b1001, b1001, b1111, true, FILL },
159 { true, true, true, b0010, b1000, b1111, true, COPY },
160 { true, true, true, b1001, b1001, b1111, true, COPY },
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td381 def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
388 def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
402 def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
478 def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
494 def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
510 def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
526 def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
675 def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
700 def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
701 def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td457 class V6_vS32b_nt_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1111>;
474 class V6_vS32b_nt_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1111>;
644 class V6_vS32b_nt_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1111>;
661 class V6_vS32b_nt_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1111>;
739 class V6_vS32b_nt_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1111>;
833 class V6_vlutvwh_oracc_enc : Enc_COPROC_VX_4op_r<0b1111>;
/external/mp4parser/isoparser/src/main/java/com/googlecode/mp4parser/boxes/mp4/objectdescriptors/
DObjectDescriptor.java_bak30 const bit(5) reserved=0b1111.1;
/external/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td433 let Opcode = 0b1111;
461 let Opcode = 0b1111;
512 let Opcode = 0b1111;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td433 let Opcode = 0b1111;
461 let Opcode = 0b1111;
512 let Opcode = 0b1111;
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt391 # VMOV cmode=0b1111 op=1 is UNDEFINED
396 # VMOV cmode=0b1111 op=1 is UNDEFINED
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt391 # VMOV cmode=0b1111 op=1 is UNDEFINED
396 # VMOV cmode=0b1111 op=1 is UNDEFINED
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dapint-add.ll46 ;; (x & 0b1111..0) + 1 -> x | 1
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td283 defm : int_cond_alias<"vc", 0b1111>;
309 defm : fp_cond_alias<"o", 0b1111>;
332 defm : cp_cond_alias<"012", 0b1111>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td283 defm : int_cond_alias<"vc", 0b1111>;
309 defm : fp_cond_alias<"o", 0b1111>;
332 defm : cp_cond_alias<"012", 0b1111>;

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