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/external/libopus/silk/
Dmacros.h44 #define silk_SMULWB(a32, b32) ((opus_int32)(((a32) * (opus_int64)((opus_int16)(b32))) >>… argument
46 …lk_SMULWB(a32, b32) ((((a32) >> 16) * (opus_int32)((opus_int16)(b32))) + ((((a32) & 0x0… argument
51 #define silk_SMLAWB(a32, b32, c32) ((opus_int32)((a32) + (((b32) * (opus_int64)((opus_int16)(… argument
53 #define silk_SMLAWB(a32, b32, c32) ((a32) + ((((b32) >> 16) * (opus_int32)((opus_int16)(c32))… argument
58 #define silk_SMULWT(a32, b32) ((opus_int32)(((a32) * (opus_int64)((b32) >> 16)) >> 16)) argument
60 #define silk_SMULWT(a32, b32) (((a32) >> 16) * ((b32) >> 16) + ((((a32) & 0x0000FFFF) * … argument
65 #define silk_SMLAWT(a32, b32, c32) ((opus_int32)((a32) + (((b32) * ((opus_int64)(c32) >> 16))… argument
67 #define silk_SMLAWT(a32, b32, c32) ((a32) + (((b32) >> 16) * ((c32) >> 16)) + ((((b32) & 0x00… argument
71 #define silk_SMULBB(a32, b32) ((opus_int32)((opus_int16)(a32)) * (opus_int32)((opus_int1… argument
74 #define silk_SMLABB(a32, b32, c32) ((a32) + ((opus_int32)((opus_int16)(b32))) * (opus_int32)(… argument
[all …]
DMacroDebug.h150 static OPUS_INLINE opus_int32 silk_ADD_SAT32_(opus_int32 a32, opus_int32 b32, char *file, int line){ in silk_ADD_SAT32_() argument
152 res = ((((opus_uint32)(a32) + (opus_uint32)(b32)) & 0x80000000) == 0 ? \ in silk_ADD_SAT32_()
153 ((((a32) & (b32)) & 0x80000000) != 0 ? silk_int32_MIN : (a32)+(b32)) : \ in silk_ADD_SAT32_()
154 ((((a32) | (b32)) & 0x80000000) == 0 ? silk_int32_MAX : (a32)+(b32)) ); in silk_ADD_SAT32_()
155 if ( res != silk_SAT32( (opus_int64)a32 + (opus_int64)b32 ) ) in silk_ADD_SAT32_()
157 fprintf (stderr, "silk_ADD_SAT32(%d, %d) in %s: line %d\n", a32, b32, file, line); in silk_ADD_SAT32_()
211 static OPUS_INLINE opus_int32 silk_SUB_SAT32_( opus_int32 a32, opus_int32 b32, char *file, int line… in silk_SUB_SAT32_() argument
213 res = ((((opus_uint32)(a32)-(opus_uint32)(b32)) & 0x80000000) == 0 ? \ in silk_SUB_SAT32_()
214 (( (a32) & ((b32)^0x80000000) & 0x80000000) ? silk_int32_MIN : (a32)-(b32)) : \ in silk_SUB_SAT32_()
215 ((((a32)^0x80000000) & (b32) & 0x80000000) ? silk_int32_MAX : (a32)-(b32)) ); in silk_SUB_SAT32_()
[all …]
DMacroCount.h54 static OPUS_INLINE opus_int32 silk_MUL(opus_int32 a32, opus_int32 b32){ in silk_MUL() argument
57 ret = a32 * b32; in silk_MUL()
62 static OPUS_INLINE opus_uint32 silk_MUL_uint(opus_uint32 a32, opus_uint32 b32){ in silk_MUL_uint() argument
65 ret = a32 * b32; in silk_MUL_uint()
69 static OPUS_INLINE opus_int32 silk_MLA(opus_int32 a32, opus_int32 b32, opus_int32 c32){ in silk_MLA() argument
72 ret = a32 + b32 * c32; in silk_MLA()
77 static OPUS_INLINE opus_int32 silk_MLA_uint(opus_uint32 a32, opus_uint32 b32, opus_uint32 c32){ in silk_MLA_uint() argument
80 ret = a32 + b32 * c32; in silk_MLA_uint()
85 static OPUS_INLINE opus_int32 silk_SMULWB(opus_int32 a32, opus_int32 b32){ in silk_SMULWB() argument
88 …ret = (a32 >> 16) * (opus_int32)((opus_int16)b32) + (((a32 & 0x0000FFFF) * (opus_int32)((opus_int1… in silk_SMULWB()
[all …]
DInlines.h99 const opus_int32 b32, /* I denominator (Q0) */ in silk_DIV32_varQ() argument
106 silk_assert( b32 != 0 ); in silk_DIV32_varQ()
112 b_headrm = silk_CLZ32( silk_abs(b32) ) - 1; in silk_DIV32_varQ()
113 …b32_nrm = silk_LSHIFT(b32, b_headrm); /* Q: b_headrm … in silk_DIV32_varQ()
144 const opus_int32 b32, /* I denominator (Q0) */ in silk_INVERSE32_varQ() argument
151 silk_assert( b32 != 0 ); in silk_INVERSE32_varQ()
155 b_headrm = silk_CLZ32( silk_abs(b32) ) - 1; in silk_INVERSE32_varQ()
156 …b32_nrm = silk_LSHIFT(b32, b_headrm); /* Q: b_headrm … in silk_INVERSE32_varQ()
DSigProc_FIX.h427 #define silk_MUL(a32, b32) ((a32) * (b32)) argument
430 #define silk_MUL_uint(a32, b32) silk_MUL(a32, b32) argument
433 #define silk_MLA(a32, b32, c32) silk_ADD32((a32),((b32) * (c32))) argument
436 #define silk_MLA_uint(a32, b32, c32) silk_MLA(a32, b32, c32) argument
439 #define silk_SMULTT(a32, b32) (((a32) >> 16) * ((b32) >> 16)) argument
442 #define silk_SMLATT(a32, b32, c32) silk_ADD32((a32),((b32) >> 16) * ((c32) >> 16)) argument
447 #define silk_SMULL(a32, b32) ((opus_int64)(a32) * /*(opus_int64)*/(b32)) argument
474 #define silk_SMLABB_ovflw(a32, b32, c32) (silk_ADD32_ovflw((a32) , ((opus_int32)((opus_int16)(b3… argument
477 #define silk_DIV32(a32, b32) ((opus_int32)((a32) / (b32))) argument
631 #define silk_SMMUL(a32, b32) (opus_int32)silk_RSHIFT64(silk_SMULL((a32), (b32)), 32) argument
/external/mesa3d/src/gallium/drivers/nouveau/codegen/lib/
Dgk104.asm16 long xor b32 $r2 $r2 0x1f
17 long mov b32 $r3 0x1
18 shl b32 $r2 $r3 clamp $r2
32 mov b32 $r3 $r0
37 $p0 sub b32 $r1 $r1 $r2
39 $p0 add b32 $r0 $r0 0x1
41 $p0 sub b32 $r1 $r1 $r2
42 $p0 add b32 $r0 $r0 0x1
58 long xor b32 $r2 $r2 0x1f
59 long mov b32 $r3 0x1
[all …]
Dgk110.asm16 xor b32 $r2 $r2 0x1f
17 mov b32 $r3 0x1
18 shl b32 $r2 $r3 clamp $r2
32 mov b32 $r3 $r0
37 $p0 sub b32 $r1 $r1 $r2
39 $p0 add b32 $r0 $r0 0x1
41 $p0 sub b32 $r1 $r1 $r2
42 $p0 add b32 $r0 $r0 0x1
58 xor b32 $r2 $r2 0x1f
59 mov b32 $r3 0x1
[all …]
Dgf100.asm15 xor b32 $r2 $r2 0x1f
16 mov b32 $r3 0x1
17 shl b32 $r2 $r3 clamp $r2
29 mov b32 $r3 $r0
34 $p0 sub b32 $r1 $r1 $r2
35 $p0 add b32 $r0 $r0 0x1
37 $p0 sub b32 $r1 $r1 $r2
38 $p0 add b32 $r0 $r0 0x1
53 xor b32 $r2 $r2 0x1f
54 mov b32 $r3 0x1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Df16x2-instructions.ll19 ; CHECK: mov.b32 [[R:%hh[0-9+]]], [[T]];
20 ; CHECK: st.param.b32 [func_retval0+0], [[R]];
27 ; CHECK: ld.param.b32 [[A:%hh[0-9]+]], [test_extract_0_param_0];
28 ; CHECK: mov.b32 {[[R:%h[0-9]+]], %tmp_hi}, [[A]];
37 ; CHECK: ld.param.b32 [[A:%hh[0-9]+]], [test_extract_1_param_0];
38 ; CHECK: mov.b32 {%tmp_lo, [[R:%h[0-9]+]]}, [[A]];
47 ; CHECK-DAG: ld.param.b32 [[A:%hh[0-9]+]], [test_extract_i_param_0];
50 ; CHECK-DAG: mov.b32 {[[E0:%h[0-9]+]], [[E1:%h[0-9]+]]}, [[A]];
60 ; CHECK-DAG: ld.param.b32 [[A:%hh[0-9]+]], [test_fadd_param_0];
61 ; CHECK-DAG: ld.param.b32 [[B:%hh[0-9]+]], [test_fadd_param_1];
[all …]
Denvreg.ll40 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg0
42 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1
44 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2
46 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg3
48 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg4
50 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg5
52 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg6
54 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg7
56 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg8
58 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg9
[all …]
Dparam-load-store.ll23 ; CHECK: .func (.param .b32 func_retval0)
25 ; CHECK-NEXT: .param .b32 test_i1_param_0
30 ; CHECK: and.b32 [[C:%r[0-9]+]], [[B]], 1;
31 ; CHECK: .param .b32 param0;
32 ; CHECK: st.param.b32 [param0+0], [[C]]
33 ; CHECK: .param .b32 retval0;
36 ; CHECK: ld.param.b32 [[R8:%r[0-9]+]], [retval0+0];
37 ; CHECK: and.b32 [[R:%r[0-9]+]], [[R8]], 1;
38 ; CHECK: st.param.b32 [func_retval0+0], [[R]];
47 ; CHECK: .func (.param .b32 func_retval0)
[all …]
Drotate.ll5 declare i32 @llvm.nvvm.rotate.b32(i32, i32)
12 ; SM20: shl.b32
14 ; SM20: shr.b32
16 ; SM35: shf.l.wrap.b32
17 %val = tail call i32 @llvm.nvvm.rotate.b32(i32 %a, i32 %b)
28 ; SM35: shf.l.wrap.b32
29 ; SM35: shf.l.wrap.b32
41 ; SM35: shf.r.wrap.b32
42 ; SM35: shf.r.wrap.b32
50 ; SM20: shl.b32
[all …]
Dtexsurf-queries.ll19 ; SM20: txq.width.b32
20 ; SM30: txq.width.b32
30 ; SM20: txq.width.b32 %r{{[0-9]+}}, [tex0]
31 ; SM30: txq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
40 ; SM20: txq.height.b32
41 ; SM30: txq.height.b32
51 ; SM20: txq.height.b32 %r{{[0-9]+}}, [tex0]
52 ; SM30: txq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
61 ; SM20: suq.width.b32
62 ; SM30: suq.width.b32
[all …]
Dfns.ll11 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], [[BASE]], [[OFFSET]];
13 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], [[BASE]], 0;
16 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], 1, [[OFFSET]];
18 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], 1, 0;
22 ; CHECK: fns.b32 {{%r[0-9]+}}, 2, [[BASE]], [[OFFSET]];
24 ; CHECK: fns.b32 {{%r[0-9]+}}, 2, [[BASE]], 0;
27 ; CHECK: fns.b32 {{%r[0-9]+}}, 2, 1, [[OFFSET]];
29 ; CHECK: fns.b32 {{%r[0-9]+}}, 2, 1, 0;
Dshfl.ll18 ; CHECK: shfl.down.b32 [[OUT:%r[0-9]+]], [[IN]], 1, 2;
56 ; CHECK: shfl.down.b32 [[OUT:%f[0-9]+]], [[IN]], 5, 6;
65 ; CHECK: shfl.up.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 1, 2;
69 ; CHECK: shfl.up.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 3, 4;
73 ; CHECK: shfl.bfly.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 5, 6;
77 ; CHECK: shfl.bfly.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 7, 8;
81 ; CHECK: shfl.idx.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 9, 10;
85 ; CHECK: shfl.idx.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 11, 12;
/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll40 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg0
42 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1
44 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2
46 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg3
48 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg4
50 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg5
52 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg6
54 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg7
56 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg8
58 ; CHECK: mov.b32 %r{{[0-9]+}}, %envreg9
[all …]
Drotate.ll5 declare i32 @llvm.nvvm.rotate.b32(i32, i32)
12 ; SM20: shl.b32
14 ; SM20: shr.b32
16 ; SM35: shf.l.wrap.b32
17 %val = tail call i32 @llvm.nvvm.rotate.b32(i32 %a, i32 %b)
28 ; SM35: shf.l.wrap.b32
29 ; SM35: shf.l.wrap.b32
41 ; SM35: shf.r.wrap.b32
42 ; SM35: shf.r.wrap.b32
50 ; SM20: shl.b32
[all …]
Dtexsurf-queries.ll19 ; SM20: txq.width.b32
20 ; SM30: txq.width.b32
30 ; SM20: txq.width.b32 %r{{[0-9]+}}, [tex0]
31 ; SM30: txq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
40 ; SM20: txq.height.b32
41 ; SM30: txq.height.b32
51 ; SM20: txq.height.b32 %r{{[0-9]+}}, [tex0]
52 ; SM30: txq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
61 ; SM20: suq.width.b32
62 ; SM30: suq.width.b32
[all …]
Dshfl.ll18 ; CHECK: shfl.down.b32 [[OUT:%r[0-9]+]], [[IN]], 1, 2;
56 ; CHECK: shfl.down.b32 [[OUT:%f[0-9]+]], [[IN]], 5, 6;
65 ; CHECK: shfl.up.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 1, 2;
69 ; CHECK: shfl.up.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 3, 4;
73 ; CHECK: shfl.bfly.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 5, 6;
77 ; CHECK: shfl.bfly.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 7, 8;
81 ; CHECK: shfl.idx.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 9, 10;
85 ; CHECK: shfl.idx.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 11, 12;
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/NVPTX/
Ddebug-info.ll23 ; CHECK: .reg .b32 %r<6>;
701 ; CHECK: // .b32 10025 // Length of Unit
704 ; CHECK: // .b32 .debug_abbrev // Offset Into Abbrev. Section
724 ; CHECK: // .b32 .debug_line // DW_AT_stmt_list
751 ; CHECK: // .b32 1481 // DW_AT_import
755 ; CHECK: // .b32 1525 // DW_AT_import
759 ; CHECK: // .b32 1563 // DW_AT_import
763 ; CHECK: // .b32 1594 // DW_AT_import
767 ; CHECK: // .b32 1623 // DW_AT_import
771 ; CHECK: // .b32 1654 // DW_AT_import
[all …]
Dcu-range-hole.ll5 ; CHECK: .visible .func (.param .b32 func_retval0) b(
6 ; CHECK: .param .b32 b_param_0
16 ; CHECK: .visible .func (.param .b32 func_retval0) a(
17 ; CHECK: .param .b32 a_param_0
26 ; CHECK: .visible .func (.param .b32 func_retval0) d(
27 ; CHECK: .param .b32 d_param_0
145 ; CHECK: // .b32 183 // Length of Unit
148 ; CHECK: // .b32 .debug_abbrev // Offset Into Abbrev. Section
212 ; CHECK: // .b32 .debug_line // DW_AT_stmt_list
233 ; CHECK: // .b32 179 // DW_AT_type
[all …]
/external/webrtc/webrtc/common_audio/signal_processing/
Dsignal_processing_unittest.cc96 int32_t b32 = -1711; in TEST_F() local
108 EXPECT_EQ(4, WebRtcSpl_NormW16(b32)); in TEST_F()
122 EXPECT_EQ(109410, WebRtcSpl_AddSatW32(a32, b32)); in TEST_F()
123 EXPECT_EQ(112832, WebRtcSpl_SubSatW32(a32, b32)); in TEST_F()
126 b32 = 0x80000000; in TEST_F()
128 EXPECT_EQ(static_cast<int>(0x80000000), WebRtcSpl_AddSatW32(a32, b32)); in TEST_F()
130 b32 = 0x7fffffff; in TEST_F()
131 EXPECT_EQ(0x7fffffff, WebRtcSpl_AddSatW32(a32, b32)); in TEST_F()
133 b32 = 0x80000000; in TEST_F()
134 EXPECT_EQ(0x7fffffff, WebRtcSpl_SubSatW32(a32, b32)); in TEST_F()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PTX/
Dparameter-order.ll3 …c (.reg .b32 %ret{{[0-9]+}}) test_parameter_order (.reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dopt-addr-mode-subreg-use.ll91 br i1 %v31, label %b6, label %b32
97 br i1 undef, label %b7, label %b32
100 br i1 undef, label %b8, label %b32
103 br i1 undef, label %b9, label %b32
106 br i1 undef, label %b10, label %b32
110 br i1 %v32, label %b11, label %b32
120 br i1 %v33, label %b14, label %b32
136 br i1 undef, label %b19, label %b32
145 br i1 undef, label %b23, label %b32
151 br i1 undef, label %b24, label %b32
[all …]
Dmulti-cycle.ll46 br label %b32
48 b32: ; preds = %b32, %b18
49 %v33 = phi i32 [ 0, %b18 ], [ %v63, %b32 ]
50 %v34 = phi <16 x i32>* [ %v31, %b18 ], [ %v62, %b32 ]
51 %v35 = phi <16 x i32>* [ %v28, %b18 ], [ %v46, %b32 ]
52 %v36 = phi <16 x i32>* [ %v29, %b18 ], [ %v44, %b32 ]
53 %v37 = phi <16 x i32>* [ %v30, %b18 ], [ %v42, %b32 ]
54 %v38 = phi <16 x i32> [ %v15, %b18 ], [ %v39, %b32 ]
55 %v39 = phi <16 x i32> [ %v26, %b18 ], [ %v56, %b32 ]
56 %v40 = phi <16 x i32> [ %v27, %b18 ], [ %v51, %b32 ]
[all …]

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