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Searched refs:bankWidth (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/amd/addrlib/r800/
Degbaddrlib.cpp780 if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize) in HwlReduceBankWidthHeight()
785 if (stillGreater && pTileInfo->bankWidth > 1) in HwlReduceBankWidthHeight()
787 while (stillGreater && pTileInfo->bankWidth > 0) in HwlReduceBankWidthHeight()
789 pTileInfo->bankWidth >>= 1; in HwlReduceBankWidthHeight()
791 if (pTileInfo->bankWidth == 0) in HwlReduceBankWidthHeight()
793 pTileInfo->bankWidth = 1; in HwlReduceBankWidthHeight()
798 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
804 (tileSize * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
814 (tileSize * pipes * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
841 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
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Dciaddrlib.cpp609 pInfo->bankWidth = 1; in HwlSetupTileCfg()
963 tileInfo.banks * tileInfo.bankWidth * in HwlOptimizeTileMode()
1489 tileInfo.bankWidth * tileInfo.bankHeight; in HwlSetupTileInfo()
1500 tileInfo.bankWidth * tileInfo.bankHeight; in HwlSetupTileInfo()
1637 pCfg->info.bankWidth = 1; in ReadGbTileMode()
1730 pCfg->bankWidth = 1 << gbTileMode.f.bank_width; in ReadGbMacroTileCfg()
2183 m_macroTileTable[i].bankWidth * m_macroTileTable[i].bankHeight; in HwlGetMaxAlignments()
2231 (m_macroTileTable[stencilMacroIndex].bankWidth == in DepthStencilTileCfgMatch()
2232 m_macroTileTable[pOut->macroModeIndex].bankWidth) && in DepthStencilTileCfgMatch()
Dsiaddrlib.cpp228 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth); in ComputeBankEquation()
425 if ((pTileInfo->bankWidth == 1) && in ComputeBankEquation()
2490 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1); in HwlComputeSurfaceCoord2DFromBankPipe()
2504 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth; in HwlComputeSurfaceCoord2DFromBankPipe()
2615 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1)) in HwlPreAdjustBank()
2988 pInfo->bankWidth = 1; in HwlSetupTileCfg()
3050 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width; in ReadGbTileMode()
3498 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight; in HwlGetMaxAlignments()
3609 key.fields.bankWidth = tileConfig.info.bankWidth; in InitEquationTable()
3671 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth * in InitEquationTable()
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/external/mesa3d/src/amd/common/
Dac_surface.c432 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()
636 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw; in gfx6_compute_surface()
/external/mesa3d/src/amd/addrlib/
Daddrinterface.h150 UINT_32 bankWidth : 4; ///< Bank width member
454 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank member