| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r700_asm.c | 62 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); in r700_bytecode_alu_build()
73 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in r700_bytecode_alu_build()
97 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1); in r700_bytecode_alu_read()
98 if (alu->bank_swizzle) in r700_bytecode_alu_read()
99 alu->bank_swizzle_force = alu->bank_swizzle; in r700_bytecode_alu_read()
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| D | r600_asm.c | 449 struct alu_bank_swizzle *bs, int bank_swizzle) in check_vector() argument
458 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src]; in check_vector()
479 struct alu_bank_swizzle *bs, int bank_swizzle) in check_scalar() argument
505 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; in check_scalar()
516 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; in check_scalar()
528 int bank_swizzle[5]; in check_and_set_bank_swizzle() local
536 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force; in check_and_set_bank_swizzle()
552 bank_swizzle[i] = SQ_ALU_VEC_012; in check_and_set_bank_swizzle()
554 bank_swizzle[i] = slots[i]->bank_swizzle; in check_and_set_bank_swizzle()
556 bank_swizzle[4] = SQ_ALU_SCL_210; in check_and_set_bank_swizzle()
[all …]
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| D | eg_asm.c | 296 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in eg_bytecode_alu_build()
314 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); in eg_bytecode_alu_build()
325 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in eg_bytecode_alu_build()
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| D | r600_asm.h | 60 unsigned bank_swizzle; member
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_sched.cpp | 233 unsigned bs = n->bc.bank_swizzle; in unreserve()
261 unsigned bs = n->bc.bank_swizzle; in try_reserve()
495 n->bc.bank_swizzle = 0; in try_reserve()
498 n->bc.bank_swizzle = VEC_210; in try_reserve()
508 n->bc.bank_swizzle = bs; in try_reserve()
529 save_bs[i] = a->bc.bank_swizzle; in try_reserve()
533 a->bc.bank_swizzle = VEC_210; in try_reserve()
540 a->bc.bank_swizzle = 0; in try_reserve()
563 sblog << " bs: trying s" << i << " bs:" << a->bc.bank_swizzle in try_reserve()
569 sblog << " bs: reserved s" << i << " bs:" << a->bc.bank_swizzle in try_reserve()
[all …]
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| D | sb_bc_builder.cpp | 397 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
424 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
442 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
457 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
471 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
487 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
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| D | sb_bc_dump.cpp | 372 if (n.bc.bank_swizzle) { in dump()
375 s << " " << scl_bs[n.bc.bank_swizzle]; in dump()
377 s << " " << vec_bs[n.bc.bank_swizzle]; in dump()
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| D | sb_bc_decoder.cpp | 327 bc.bank_swizzle = iw1.get_BANK_SWIZZLE(); in decode_alu()
349 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
366 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
385 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
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| D | sb_bc.h | 380 enum bank_swizzle { enum
511 unsigned bank_swizzle:3; member
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 107 bits<3> bank_swizzle;
114 let Word1{20-18} = bank_swizzle;
165 bits<3> bank_swizzle;
173 let Word1{20-18} = bank_swizzle;
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| D | R600Packetizer.cpp | 306 AMDGPU::OpName::bank_swizzle); in addToPacket()
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle); in addToPacket()
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| D | EvergreenInstructions.td | 415 let bank_swizzle = 0;
465 BANK_SWIZZLE:$bank_swizzle),
487 BANK_SWIZZLE:$bank_swizzle),
519 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
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| D | R600Instructions.td | 99 BANK_SWIZZLE:$bank_swizzle),
103 "$pred_sel $bank_swizzle"),
142 BANK_SWIZZLE:$bank_swizzle),
147 "$pred_sel $bank_swizzle"),
183 BANK_SWIZZLE:$bank_swizzle),
189 "$bank_swizzle"),
440 let bank_swizzle = 5;
444 let bank_swizzle = 5;
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| D | R600InstrInfo.cpp | 558 AMDGPU::OpName::bank_swizzle); in fitsReadPortLimitations()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 117 bits<3> bank_swizzle;
124 let Word1{20-18} = bank_swizzle;
175 bits<3> bank_swizzle;
183 let Word1{20-18} = bank_swizzle;
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| D | R600Packetizer.cpp | 304 R600::OpName::bank_swizzle); in addToPacket()
308 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
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| D | EvergreenInstructions.td | 489 let bank_swizzle = 0;
534 BANK_SWIZZLE:$bank_swizzle),
556 BANK_SWIZZLE:$bank_swizzle),
588 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
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| D | R600Instructions.td | 110 BANK_SWIZZLE:$bank_swizzle),
114 "$pred_sel $bank_swizzle"),
153 BANK_SWIZZLE:$bank_swizzle),
158 "$pred_sel $bank_swizzle"),
194 BANK_SWIZZLE:$bank_swizzle),
200 "$bank_swizzle"),
411 let bank_swizzle = 5;
415 let bank_swizzle = 5;
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| D | R600InstrInfo.cpp | 550 R600::OpName::bank_swizzle); in fitsReadPortLimitations()
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