| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 151 surf_drm->bankw = surf_ws->u.legacy.bankw; in surf_winsys_to_drm()
193 surf_ws->u.legacy.bankw = surf_drm->bankw; in surf_drm_to_winsys()
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| D | radeon_drm_bo.c | 863 …md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_… in radeon_bo_get_metadata()
891 args.tiling_flags |= (md->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) << in radeon_bo_set_metadata()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_video.c | 153 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh; in si_vid_join_surfaces()
170 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw; in si_vid_join_surfaces()
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| D | radeon_winsys.h | 192 unsigned bankw; member
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| D | r600_texture.c | 340 metadata->u.legacy.bankw = surface->u.legacy.bankw; in r600_texture_init_metadata()
368 surf->u.legacy.bankw = metadata->u.legacy.bankw; in r600_surface_import_metadata()
1120 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw, in si_print_texture_info()
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| D | radeon_uvd.c | 1609 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw); in si_uvd_set_dt_surfaces()
1614 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw)); in si_uvd_set_dt_surfaces()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_video.c | 160 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh; in rvid_join_surfaces()
175 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw; in rvid_join_surfaces()
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| D | evergreen_state.c | 719 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; in evergreen_fill_tex_resource_words() local
798 bankw = tmp->surface.u.legacy.bankw; in evergreen_fill_tex_resource_words()
802 bankw = eg_bank_wh(bankw); in evergreen_fill_tex_resource_words()
886 S_03001C_BANK_WIDTH(bankw) | in evergreen_fill_tex_resource_words()
1109 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; in evergreen_set_color_surface_common() local
1147 bankw = rtex->surface.u.legacy.bankw; in evergreen_set_color_surface_common()
1155 bankw = eg_bank_wh(bankw); in evergreen_set_color_surface_common()
1172 S_028C74_BANK_WIDTH(bankw) | in evergreen_set_color_surface_common()
1345 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; in evergreen_init_depth_surface() local
1366 bankw = rtex->surface.u.legacy.bankw; in evergreen_init_depth_surface()
[all …]
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| D | r600_texture.c | 285 metadata->u.legacy.bankw = surface->u.legacy.bankw; in r600_texture_init_metadata()
301 surf->u.legacy.bankw = metadata->u.legacy.bankw; in r600_surface_import_metadata()
591 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw; in r600_texture_get_fmask_info()
822 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw, in r600_print_texture_info()
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| D | radeon_uvd.c | 1484 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw); in ruvd_set_dt_surfaces()
1489 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw)); in ruvd_set_dt_surfaces()
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| /external/libdrm/radeon/ |
| D | radeon_surface.c | 675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
760 switch (surf->bankw) { in eg_surface_sanity()
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
919 surf->bankw = 1; in eg_surface_best()
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
998 surf->bankw = 1; in eg_surface_best()
1013 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1019 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1321 surf->bankw = 1; in si_surface_sanity()
1399 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
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| D | radeon_surface.h | 130 uint32_t bankw; member
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.h | 83 unsigned bankw:4; /* max 8 */ member
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| D | ac_surface.c | 432 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()
629 surf->u.legacy.bankw && surf->u.legacy.bankh && in gfx6_compute_surface()
636 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw; in gfx6_compute_surface()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_radeon_winsys.h | 136 unsigned bankw; member
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| D | radv_image.c | 639 metadata->u.legacy.bankw = surface->u.legacy.bankw; in radv_init_metadata()
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 518 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); in radv_amdgpu_winsys_bo_set_metadata()
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_bo.c | 1104 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_buffer_get_metadata()
1136 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); in amdgpu_buffer_set_metadata()
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