| /external/mesa3d/src/amd/addrlib/gfx9/ |
| D | gfx9addrlib.h | 229 UINT_32 baseAlign; in HwlComputeSurfaceBaseAlign() local
233 baseAlign = GetBlockSize(swizzleMode); in HwlComputeSurfaceBaseAlign()
237 baseAlign = 256; in HwlComputeSurfaceBaseAlign()
240 return baseAlign; in HwlComputeSurfaceBaseAlign()
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| D | gfx9addrlib.cpp | 239 pOut->baseAlign = Max(numCompressBlkPerMetaBlk * 4, sizeAlign); in HwlComputeHtileInfo()
243 pOut->baseAlign = Max(pOut->baseAlign, GetBlockSize(pIn->swizzleMode)); in HwlComputeHtileInfo()
340 pOut->baseAlign = Max(numCompressBlkPerMetaBlk >> 1, sizeAlign); in HwlComputeCmaskInfo()
344 pOut->baseAlign = Max(pOut->baseAlign, GetBlockSize(pIn->swizzleMode)); in HwlComputeCmaskInfo()
685 pOut->baseAlign = HwlComputeSurfaceBaseAlign(ADDR_SW_64KB); in HwlGetMaxAlignments()
4040 pOut->baseAlign = HwlComputeSurfaceBaseAlign(pIn->swizzleMode); in HwlComputeSurfaceInfoTiled()
4044 pOut->baseAlign = Max(pOut->baseAlign, PrtAlignment); in HwlComputeSurfaceInfoTiled()
4129 … pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? (pIn->bpp / 8) : alignment; in HwlComputeSurfaceInfoLinear()
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.c | 216 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign; in amdgpu_addr_create()
306 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in gfx6_compute_level()
379 surf->htile_alignment = AddrHtileOut->baseAlign; in gfx6_compute_level()
426 surf->surf_alignment = csio->baseAlign; in gfx6_surface_settings()
870 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign); in gfx9_compute_miptree()
871 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign); in gfx9_compute_miptree()
890 surf->surf_alignment = out.baseAlign; in gfx9_compute_miptree()
924 surf->htile_alignment = hout.baseAlign; in gfx9_compute_miptree()
1020 surf->u.gfx9.fmask_alignment = fout.baseAlign; in gfx9_compute_miptree()
1051 surf->u.gfx9.cmask_alignment = cout.baseAlign; in gfx9_compute_miptree()
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| /external/mesa3d/src/amd/addrlib/ |
| D | addrinterface.h | 598 UINT_32 baseAlign; ///< Base address alignment member
908 UINT_32 baseAlign; ///< Base alignment member
1127 UINT_32 baseAlign; ///< Base alignment member
1324 UINT_32 baseAlign; ///< Base address alignment member
2310 UINT_64 baseAlign; ///< Maximum base alignment in bytes member
2470 UINT_32 baseAlign; ///< Base address alignment member
2743 UINT_32 baseAlign; ///< Base alignment member
2929 UINT_32 baseAlign; ///< Base alignment member
3138 UINT_32 baseAlign; ///< Base alignment member
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| /external/mesa3d/src/amd/addrlib/core/ |
| D | addrlib1.cpp | 1310 pOut->baseAlign = align; in ComputeHtileInfo()
1331 &pOut->baseAlign); in ComputeHtileInfo()
1397 &pOut->baseAlign, in ComputeCmaskInfo()
1839 UINT_32 baseAlign; in ComputeHtileInfo() local
1867 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo); in ComputeHtileInfo()
1875 baseAlign); in ComputeHtileInfo()
1888 SafeAssign(pBaseAlign, baseAlign); in ComputeHtileInfo()
1909 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); in ComputeCmaskBaseAlign() local
1916 baseAlign *= pTileInfo->banks; in ComputeCmaskBaseAlign()
1920 return baseAlign; in ComputeCmaskBaseAlign()
[all …]
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| D | addrlib2.cpp | 682 pOut->baseAlign = localOut.baseAlign; in ComputeFmaskInfo()
1859 ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0); in ComputeQbStereoInfo()
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| D | addrlib1.h | 246 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
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| /external/mesa3d/src/amd/addrlib/r800/ |
| D | siaddrlib.h | 156 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
196 UINT_32 baseAlign, UINT_32 pitchAlign,
227 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
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| D | egbaddrlib.cpp | 239 &pOut->baseAlign, in ComputeSurfaceInfoLinear()
282 pOut->baseAlign, in ComputeSurfaceInfoLinear()
401 &pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
430 pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
956 pOut->baseAlign = in ComputeSurfaceAlignmentsMacroTiled()
1220 *pSizeAlign = out.baseAlign; in HwlGetAlignmentInfoMacroTiled()
3203 UINT_32 baseAlign ///< [in] base alignments in ComputeHtileBytes()
3282 pOut->baseAlign = surfOut.baseAlign; in DispatchComputeFmaskInfo()
4023 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); in HwlComputeHtileBaseAlign() local
4030 baseAlign *= pTileInfo->banks; in HwlComputeHtileBaseAlign()
[all …]
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| D | egbaddrlib.h | 173 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
181 UINT_32 baseAlign, UINT_32 pitchAlign,
293 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
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| D | siaddrlib.cpp | 1241 UINT_32 baseAlign ///< [in] base alignments in HwlComputeHtileBytes()
1244 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign); in HwlComputeHtileBytes()
1653 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentLinear() argument
1808 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentMicroTiled() argument
1828 while ((physicalSliceSize % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
1851 while ((logicalSiceSizeStencil % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
3497 UINT_64 baseAlign = tileSize * pipes * m_tileTable[i].info.banks * in HwlGetMaxAlignments() local
3500 if (baseAlign > maxBaseAlign) in HwlGetMaxAlignments()
3502 maxBaseAlign = baseAlign; in HwlGetMaxAlignments()
3509 pOut->baseAlign = maxBaseAlign; in HwlGetMaxAlignments()
[all …]
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| D | ciaddrlib.cpp | 2182 UINT_64 baseAlign = tileSize * pipes * m_macroTileTable[i].banks * in HwlGetMaxAlignments() local
2185 if (baseAlign > maxBaseAlign) in HwlGetMaxAlignments()
2187 maxBaseAlign = baseAlign; in HwlGetMaxAlignments()
2193 pOut->baseAlign = maxBaseAlign; in HwlGetMaxAlignments()
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