Searched refs:base_mip (Results 1 – 6 of 6) sorted by relevance
| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 997 hw_level = iview->base_mip; in radv_image_view_make_descriptor()
1014 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip]; in radv_image_view_make_descriptor()
1016 base_level_info = &image->surface.u.legacy.level[iview->base_mip]; in radv_image_view_make_descriptor()
1020 iview->base_mip, in radv_image_view_make_descriptor()
1021 iview->base_mip, in radv_image_view_make_descriptor()
1125 iview->base_mip = range->baseMipLevel; in radv_image_view_init()
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| D | radv_meta_blit.c | 280 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip); in meta_emit_blit()
281 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip); in meta_emit_blit()
282 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip); in meta_emit_blit()
283 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip); in meta_emit_blit()
284 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip); in meta_emit_blit()
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| D | radv_device.c | 3121 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; in radv_initialise_color_surface()
3130 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false); in radv_initialise_color_surface()
3235 if (radv_vi_dcc_enabled(iview->image, iview->base_mip)) in radv_initialise_color_surface()
3282 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip); in radv_initialise_color_surface()
3296 unsigned level = iview->base_mip; in radv_initialise_ds_surface()
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| D | radv_private.h | 1462 uint32_t base_mip; member
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| D | radv_meta_clear.c | 562 iview->base_mip == 0 && in depth_view_can_fast_clear()
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| D | radv_cmd_buffer.c | 2094 range.baseMipLevel = view->base_mip; in radv_handle_subpass_image_transition()
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