/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/SkylakeServer/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/SkylakeClient/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Broadwell/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Haswell/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Generic/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Znver1/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/BtVer2/ |
D | resources-bmi1.s | 28 blsr %eax, %ecx label 29 blsr (%rax), %ecx label 31 blsr %rax, %rcx label 32 blsr (%rax), %rcx label
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/external/v8/src/ia32/ |
D | assembler-ia32.h | 1529 void blsr(Register dst, Register src) { blsr(dst, Operand(src)); } in blsr() function 1530 void blsr(Register dst, Operand src) { bmi1(0xf3, ecx, dst, src); } in blsr() function
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
D | bmi.ll | 632 ; The add here used to get shrunk, but the and did not thus hiding the blsr pattern.
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/external/llvm/lib/Target/X86/ |
D | X86InstrInfo.td | 2220 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2221 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
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/external/epid-sdk/ext/ipp/sources/include/ |
D | ia_32e.inc | 2002 blsr macro x:req, z:req 2003 %ECHO @CatStr(<blsr >, < x,>, < z >)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstrInfo.td | 2380 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2381 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
D | X86GenAsmMatcher.inc | 6529 "lsiq\006blsmsk\007blsmskl\007blsmskq\004blsr\005blsrl\005blsrq\005bndcl" 21637 { 514 /* blsr */, X86::BLSR32rr, Convert__Reg1_0__Reg1_1, 0, { MCK_GR32, MCK_GR32 }, }, 21638 { 514 /* blsr */, X86::BLSR32rm, Convert__Reg1_0__Mem325_1, 0, { MCK_GR32, MCK_Mem32 }, }, 21639 { 514 /* blsr */, X86::BLSR64rr, Convert__Reg1_0__Reg1_1, 0, { MCK_GR64, MCK_GR64 }, }, 21640 { 514 /* blsr */, X86::BLSR64rm, Convert__Reg1_0__Mem645_1, 0, { MCK_GR64, MCK_Mem64 }, },
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