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Searched refs:bneg (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dshift_no_and.ll90 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
95 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
99 ; CHECK: bneg.b
109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
114 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
118 ; CHECK: bneg.h
128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
133 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
137 ; CHECK: bneg.w
147 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1)
[all …]
D3r-b.ll327 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
332 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
337 ; CHECK: bneg.b
349 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
354 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
359 ; CHECK: bneg.h
371 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
376 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
381 ; CHECK: bneg.w
393 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dshift_constant_pool.ll41 …%0 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> <i32 2147483649, i32 2147483649, i32 7, i32 7…
46 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
Dbitwise.ll1397 ; CHECK-DAG: bneg.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1414 ; CHECK-DAG: bneg.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1431 ; CHECK-DAG: bneg.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1448 ; CHECK-DAG: bneg.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/llvm/test/CodeGen/Mips/msa/
D3r-b.ll327 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
332 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
337 ; CHECK: bneg.b
349 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
354 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
359 ; CHECK: bneg.h
371 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
376 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
381 ; CHECK: bneg.w
393 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dbitwise.ll1397 ; CHECK-DAG: bneg.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1414 ; CHECK-DAG: bneg.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1431 ; CHECK-DAG: bneg.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1448 ; CHECK-DAG: bneg.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Sparc/
Dsparc64-ctrl-instructions.s48 ! CHECK: bneg %xcc, .BB0 ! encoding: [0x0c,0b01101AAA,A,A]
50 bneg %xcc, .BB0
280 ! CHECK: bneg,a %icc, .BB0 ! encoding: [0x2c,0b01001AAA,A,A]
282 bneg,a %icc, .BB0
336 ! CHECK: bneg,pn %icc, .BB0 ! encoding: [0x0c,0b01000AAA,A,A]
338 bneg,pn %icc, .BB0
392 ! CHECK: bneg,a,pn %icc, .BB0 ! encoding: [0x2c,0b01000AAA,A,A]
394 bneg,a,pn %icc, .BB0
448 ! CHECK: bneg %icc, .BB0 ! encoding: [0x0c,0b01001AAA,A,A]
450 bneg,pt %icc, .BB0
[all …]
Dsparc-ctrl-instructions.s115 ! CHECK: bneg .BB0 ! encoding: [0x0c,0b10AAAAAA,A,A]
117 bneg .BB0
319 ! CHECK: bneg,a .BB0 ! encoding: [0x2c,0b10AAAAAA,A,A]
321 bneg,a .BB0
/external/llvm/test/MC/Sparc/
Dsparc64-ctrl-instructions.s48 ! CHECK: bneg %xcc, .BB0 ! encoding: [0x0c,0b01101AAA,A,A]
50 bneg %xcc, .BB0
280 ! CHECK: bneg,a %icc, .BB0 ! encoding: [0x2c,0b01001AAA,A,A]
282 bneg,a %icc, .BB0
336 ! CHECK: bneg,pn %icc, .BB0 ! encoding: [0x0c,0b01000AAA,A,A]
338 bneg,pn %icc, .BB0
392 ! CHECK: bneg,a,pn %icc, .BB0 ! encoding: [0x2c,0b01000AAA,A,A]
394 bneg,a,pn %icc, .BB0
448 ! CHECK: bneg %icc, .BB0 ! encoding: [0x0c,0b01001AAA,A,A]
450 bneg,pt %icc, .BB0
[all …]
Dsparc-ctrl-instructions.s115 ! CHECK: bneg .BB0 ! encoding: [0x0c,0b10AAAAAA,A,A]
117 bneg .BB0
319 ! CHECK: bneg,a .BB0 ! encoding: [0x2c,0b10AAAAAA,A,A]
321 bneg,a .BB0
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs58 0x7a,0x98,0x58,0x0d = bneg.b $w0, $w11, $w24
59 0x7a,0xa4,0x87,0x0d = bneg.h $w28, $w16, $w4
60 0x7a,0xd3,0xd0,0xcd = bneg.w $w3, $w26, $w19
61 0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s59 # CHECK: bneg.b $w0, $w11, $w24 # encoding: [0x7a,0x98,0x58,0x0d]
60 # CHECK: bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d]
61 # CHECK: bneg.w $w3, $w26, $w19 # encoding: [0x7a,0xd3,0xd0,0xcd]
62 # CHECK: bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d]
302 bneg.b $w0, $w11, $w24
303 bneg.h $w28, $w16, $w4
304 bneg.w $w3, $w26, $w19
305 bneg.d $w13, $w29, $w15
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_3r.s59 # CHECK: bneg.b $w0, $w11, $w24 # encoding: [0x7a,0x98,0x58,0x0d]
60 # CHECK: bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d]
61 # CHECK: bneg.w $w3, $w26, $w19 # encoding: [0x7a,0xd3,0xd0,0xcd]
62 # CHECK: bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d]
302 bneg.b $w0, $w11, $w24
303 bneg.h $w28, $w16, $w4
304 bneg.w $w3, $w26, $w19
305 bneg.d $w13, $w29, $w15
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt59 0x7a 0x98 0x58 0x0d # CHECK: bneg.b $w0, $w11, $w24
60 0x7a 0xa4 0x87 0x0d # CHECK: bneg.h $w28, $w16, $w4
61 0x7a 0xd3 0xd0 0xcd # CHECK: bneg.w $w3, $w26, $w19
62 0x7a 0xef 0xeb 0x4d # CHECK: bneg.d $w13, $w29, $w15
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt59 0x7a 0x98 0x58 0x0d # CHECK: bneg.b $w0, $w11, $w24
60 0x7a 0xa4 0x87 0x0d # CHECK: bneg.h $w28, $w16, $w4
61 0x7a 0xd3 0xd0 0xcd # CHECK: bneg.w $w3, $w26, $w19
62 0x7a 0xef 0xeb 0x4d # CHECK: bneg.d $w13, $w29, $w15
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc.txt120 # CHECK: bneg 4194303
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Sparc/
Dsparc.txt120 # CHECK: bneg 4194303
/external/capstone/arch/Sparc/
DSparcGenAsmWriter.inc1322 AsmString = "bneg $\x01";
1436 AsmString = "bneg,a $\x01";
1842 AsmString = "bneg,a,pn %icc, $\x01";
1956 AsmString = "bneg,pn %icc, $\x01";
2070 AsmString = "bneg,a,pn %xcc, $\x01";
2184 AsmString = "bneg,pn %xcc, $\x01";
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td280 // bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b
DMipsMSAInstrInfo.td1695 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1696 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1697 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1698 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
DMipsScheduleGeneric.td913 // bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b
/external/toybox/toys/pending/
Dbc.c1396 int aneg, bneg, neg; in bc_num_s() local
1412 bneg = b->neg; in bc_num_s()
1418 b->neg = bneg; in bc_num_s()
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1697 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1698 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1699 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1700 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4861 "bnec\006bneg.b\006bneg.d\006bneg.h\006bneg.w\007bnegi.b\007bnegi.d\007b"
5418 …{ 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
5419 …{ 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
5420 …{ 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
5421 …{ 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
8386 { Feature_HasStdEnc|Feature_HasMSA, 1428 /* bneg.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8387 { Feature_HasStdEnc|Feature_HasMSA, 1435 /* bneg.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8388 { Feature_HasStdEnc|Feature_HasMSA, 1442 /* bneg.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8389 { Feature_HasStdEnc|Feature_HasMSA, 1449 /* bneg.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/bigdec/
DDiagBigDecimalTest.java129 private static final byte bneg = -1; field in DiagBigDecimalTest
2749 … TestFmwk.assertTrue("byv012", ((bneg))==((new android.icu.math.BigDecimal(bneg)).byteValue())); in diagbyteValue()
2762 …TestFmwk.assertTrue("byv028", ((bneg))==((new android.icu.math.BigDecimal(bneg)).byteValueExact())… in diagbyteValue()

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