| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 76 int r = radv_amdgpu_bo_va_op(bo->ws, range->bo->bo, range->bo_offset, in radv_amdgpu_winsys_virtual_map()
92 int r = radv_amdgpu_bo_va_op(bo->ws, range->bo->bo, range->bo_offset, in radv_amdgpu_winsys_virtual_unmap()
133 struct radeon_winsys_bo *_bo, uint64_t bo_offset) in radv_amdgpu_winsys_bo_virtual_bind() argument
178 …es[first].bo == bo && (!bo || offset - bo_offset == parent->ranges[first].offset - parent->ranges[… in radv_amdgpu_winsys_bo_virtual_bind()
181 bo_offset = parent->ranges[first].bo_offset; in radv_amdgpu_winsys_bo_virtual_bind()
186 …nges[last].bo == bo && (!bo || offset - bo_offset == parent->ranges[last].offset - parent->ranges[… in radv_amdgpu_winsys_bo_virtual_bind()
239 parent->ranges[new_idx].bo_offset = bo_offset; in radv_amdgpu_winsys_bo_virtual_bind()
326 bo->ranges[0].bo_offset = 0; in radv_amdgpu_winsys_bo_create()
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| D | radv_amdgpu_bo.h | 39 uint64_t bo_offset; member
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| /external/mesa3d/src/intel/vulkan/ |
| D | genX_cmd_buffer.c | 1591 uint32_t bo_offset = cmd_buffer->state.compute.num_workgroups.offset; in emit_binding_table() local
1600 format, bo_offset, 12, 1); in emit_binding_table()
1603 add_surface_state_reloc(cmd_buffer, surface_state, bo, bo_offset); in emit_binding_table()
2422 uint32_t bo_offset = buffer->offset + offset; in load_indirect_parameters() local
2424 emit_lrm(batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset); in load_indirect_parameters()
2429 emit_lrm(batch, CS_GPR(0), bo, bo_offset + 4); in load_indirect_parameters()
2435 emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4); in load_indirect_parameters()
2438 emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4); in load_indirect_parameters()
2441 emit_lrm(batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8); in load_indirect_parameters()
2444 emit_lrm(batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12); in load_indirect_parameters()
[all …]
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| D | anv_intel.c | 99 image->planes[0].bo_offset = 0; in anv_CreateDmaBufImageINTEL()
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| D | anv_image.c | 636 image->planes[plane].bo_offset = 0; in anv_image_bind_memory_plane()
641 image->planes[plane].bo_offset = memory_offset; in anv_image_bind_memory_plane()
936 const uint64_t address = image->planes[plane].bo_offset + surface->offset; in anv_image_fill_surface_state()
938 0 : (image->planes[plane].bo_offset + aux_surface->offset); in anv_image_fill_surface_state()
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| D | anv_android.c | 186 assert(image->planes[0].bo_offset == 0); in anv_image_from_gralloc()
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| D | anv_blorp.c | 208 .offset = image->planes[plane].bo_offset + surface->offset, in get_blorp_surf_for_anv_image()
218 .offset = image->planes[plane].bo_offset + aux_surface->offset, in get_blorp_surf_for_anv_image()
1611 .offset = image->planes[0].bo_offset + in anv_image_copy_to_shadow()
1673 .offset = image->planes[0].bo_offset + in anv_gen8_hiz_op_resolve()
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| D | anv_private.h | 2469 VkDeviceSize bo_offset; member
2537 .offset = image->planes[plane].bo_offset + in anv_image_get_clear_color_addr()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_shader.c | 317 if (s->bo_offset - offset >= shader->code_size) { in radv_alloc_shader_memory()
319 shader->bo_offset = offset; in radv_alloc_shader_memory()
324 offset = align_u64(s->bo_offset + s->code_size, 256); in radv_alloc_shader_memory()
328 shader->bo_offset = offset; in radv_alloc_shader_memory()
351 shader->bo_offset = 0; in radv_alloc_shader_memory()
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| D | radv_shader.h | 47 uint64_t bo_offset; member
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| D | radv_cmd_buffer.c | 701 va = radv_buffer_get_va(shader->bo) + shader->bo_offset; in radv_emit_shader_prefetch()
730 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; in radv_emit_hw_vs()
764 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; in radv_emit_hw_es()
777 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; in radv_emit_hw_ls()
798 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; in radv_emit_hw_hs()
946 va = radv_buffer_get_va(gs->bo) + gs->bo_offset; in radv_emit_geometry_shader()
997 va = radv_buffer_get_va(ps->bo) + ps->bo_offset; in radv_emit_fragment_shader()
1707 unsigned bo_offset; in radv_flush_push_descriptors() local
1711 &bo_offset)) in radv_flush_push_descriptors()
1715 set->va += bo_offset; in radv_flush_push_descriptors()
[all …]
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| D | radv_radeon_winsys.h | 218 struct radeon_winsys_bo *bo, uint64_t bo_offset);
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| D | radv_debug.c | 383 start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset; in radv_dump_annotated_shader()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_wm_surface_state.c | 1588 uint32_t bo_offset; in brw_upload_cs_work_groups_surface() local
1597 &bo_offset); in brw_upload_cs_work_groups_surface()
1600 bo_offset = brw->compute.num_work_groups_offset; in brw_upload_cs_work_groups_surface()
1604 bo, bo_offset, in brw_upload_cs_work_groups_surface()
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| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nve4_compute.c | 648 uint32_t length, uint32_t bo_offset) in nve4_upload_indirect_desc() argument
662 nouveau_pushbuf_data(push, res->bo, bo_offset, in nve4_upload_indirect_desc()
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