| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 35 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
68 unsigned bpe) in surf_level_winsys_to_drm() argument
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe; in surf_level_winsys_to_drm()
80 unsigned bpe) in surf_level_drm_to_winsys() argument
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes); in surf_level_drm_to_winsys()
92 unsigned flags, unsigned bpe, in surf_winsys_to_drm() argument
108 surf_drm->bpe = bpe; in surf_winsys_to_drm()
158 bpe * surf_drm->nsamples); in surf_winsys_to_drm()
185 surf_ws->bpe = surf_drm->bpe; in surf_drm_to_winsys()
202 surf_drm->bpe * surf_drm->nsamples); in surf_drm_to_winsys()
[all …]
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| /external/libdrm/radeon/ |
| D | radeon_surface.c | 169 unsigned bpe, unsigned level, in surf_minify() argument
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
351 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_1d()
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| D | radeon_surface.h | 119 uint32_t bpe; member
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_surface.c | 65 unsigned flags, unsigned bpe, in amdgpu_surface_init() argument
78 surf->bpe = bpe; in amdgpu_surface_init()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 57 if (rdst->surface.bpe != rsrc->surface.bpe) in r600_prepare_for_dma_blit()
180 rtex->surface.bpe; in r600_texture_get_offset()
193 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
210 unsigned i, bpe, flags = 0; in r600_init_surface() local
217 bpe = 4; /* stencil is allocated separately on evergreen */ in r600_init_surface()
219 bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
220 assert(util_is_power_of_two(bpe)); in r600_init_surface()
248 r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe, in r600_init_surface()
255 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) { in r600_init_surface()
259 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe; in r600_init_surface()
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| D | radeon_vce.c | 230 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in rvce_frame_offset()
453 cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in rvce_create_encoder()
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| D | r600_state.c | 2980 bpp = rdst->surface.bpe; in r600_dma_copy()
2981 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; in r600_dma_copy()
2982 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; in r600_dma_copy()
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| D | evergreen_state.c | 3840 bpp = rdst->surface.bpe; in evergreen_dma_copy()
3841 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; in evergreen_dma_copy()
3842 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; in evergreen_dma_copy()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 57 if (rdst->surface.bpe != rsrc->surface.bpe) in si_prepare_for_dma_blit()
188 *stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe; in r600_texture_get_offset()
200 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
203 rtex->surface.bpe; in r600_texture_get_offset()
216 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
235 unsigned i, bpe, flags = 0; in r600_init_surface() local
242 bpe = 4; /* stencil is allocated separately on evergreen */ in r600_init_surface()
244 bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
245 assert(util_is_power_of_two(bpe)); in r600_init_surface()
260 bpe = 4; in r600_init_surface()
[all …]
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| D | radeon_vce_40_2_2.c | 91 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
92 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
321 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
322 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce_52.c | 183 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
184 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
187 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
188 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
259 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
260 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
267 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
268 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce.c | 226 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in si_vce_frame_offset()
229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
463 align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in si_vce_create_encoder()
466 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
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| D | radeon_vce_50.c | 128 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
129 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vcn_enc.c | 279 align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in radeon_create_encoder()
281 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in radeon_create_encoder()
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| D | radeon_winsys.h | 630 unsigned flags, unsigned bpe,
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.c | 404 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
536 switch (surf->bpe) { in gfx6_compute_surface()
548 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx6_compute_surface()
657 if (surf->bpe == 2) in gfx6_compute_surface()
662 if (surf->bpe == 1) in gfx6_compute_surface()
664 else if (surf->bpe == 2) in gfx6_compute_surface()
666 else if (surf->bpe == 4) in gfx6_compute_surface()
1076 switch (surf->bpe) { in gfx9_compute_surface()
1087 AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx9_compute_surface()
1185 surf->bpe * 8, &displayable); in gfx9_compute_surface()
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| D | ac_surface.h | 156 unsigned bpe:5; member
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| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| D | ProfileVerifierPass.cpp | 247 const_pred_iterator bpi = pred_begin(BB), bpe = pred_end(BB); in recurseBasicBlock() local
249 if (bpi == bpe) { in recurseBasicBlock()
253 for (;bpi != bpe; ++bpi) { in recurseBasicBlock()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 83 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format)); in radv_init_surface()
85 if (surface->bpe == 3) { in radv_init_surface()
86 surface->bpe = 4; in radv_init_surface()
644 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; in radv_init_metadata()
685 fmask.bpe = 1; in radv_image_get_fmask_info()
688 fmask.bpe = 4; in radv_image_get_fmask_info()
843 if (image->surface.bpe > 8 && image->info.samples == 1) { in radv_image_can_enable_cmask()
1251 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe; in radv_GetImageSubresourceLayout()
1259 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe; in radv_GetImageSubresourceLayout()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_dma.c | 270 bpp = rdst->surface.bpe; in si_dma_copy()
271 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; in si_dma_copy()
272 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; in si_dma_copy()
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| D | si_clear.c | 75 if (rtex->surface.bpe == 16) { in si_set_clear_color()
305 switch (rtex->surface.bpe) { in si_set_optimal_micro_tile_mode()
318 switch (rtex->surface.bpe) { in si_set_optimal_micro_tile_mode()
478 if (tex->surface.bpe > 8) { in si_do_fast_color_clear()
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| D | si_state_binning.c | 80 sum += rtex->surface.bpe; in si_get_color_bin_size()
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| D | cik_sdma.c | 126 return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) | in encode_tile_info()
149 unsigned bpp = rdst->surface.bpe; in cik_sdma_copy_texture()
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| D | si_blit.c | 912 unsigned blocksize = rsrc->surface.bpe; in si_resource_copy_region()
955 unsigned blocksize = rsrc->surface.bpe; in si_resource_copy_region()
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| /external/python/cpython3/Lib/concurrent/futures/ |
| D | process.py | 378 bpe = BrokenProcessPool("A process in the process pool was "
382 bpe.__cause__ = _RemoteTraceback(
386 work_item.future.set_exception(bpe)
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