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Searched refs:brw_emit_pipe_control_flush (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c135 brw_emit_pipe_control_flush(brw, 0); in brw_emit_pipe_control()
227 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) in brw_emit_pipe_control_flush() function
295 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in brw_emit_depth_stall_flushes()
296 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH); in brw_emit_depth_stall_flushes()
297 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in brw_emit_depth_stall_flushes()
420 brw_emit_pipe_control_flush(brw, in brw_emit_post_sync_nonzero_flush()
524 brw_emit_pipe_control_flush(brw, flags); in brw_emit_end_of_pipe_sync()
560 brw_emit_pipe_control_flush(brw, flags); in brw_emit_mi_flush()
Dgen8_multisample_state.c41 brw_emit_pipe_control_flush(brw, in gen10_emit_wa_cs_stall_flush()
66 brw_emit_pipe_control_flush(brw, in gen10_emit_wa_lri_to_cache_mode_zero()
Dgen7_l3_state.c87 brw_emit_pipe_control_flush(brw, in setup_l3_config()
106 brw_emit_pipe_control_flush(brw, in setup_l3_config()
116 brw_emit_pipe_control_flush(brw, in setup_l3_config()
Dbrw_conditional_render.c66 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_overflow_query()
88 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_occlusion_query()
Dgen8_depth_state.c328 brw_emit_pipe_control_flush(brw, in gen8_write_pma_stall_bits()
342 brw_emit_pipe_control_flush(brw, in gen8_write_pma_stall_bits()
Dbrw_blorp.c436 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
446 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
1579 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1605 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1609 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in intel_hiz_exec()
1635 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1638 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1655 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
Dbrw_program.c312 brw_emit_pipe_control_flush(brw, bits); in brw_memory_barrier()
323 brw_emit_pipe_control_flush(brw, in brw_blend_barrier()
326 brw_emit_pipe_control_flush(brw, in brw_blend_barrier()
329 brw_emit_pipe_control_flush(brw, in brw_blend_barrier()
Dbrw_pipe_control.h78 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
Dbrw_misc_state.c461 brw_emit_pipe_control_flush(brw, in brw_emit_select_pipeline()
468 brw_emit_pipe_control_flush(brw, in brw_emit_select_pipeline()
733 brw_emit_pipe_control_flush(brw, in brw_upload_state_base_address()
Dintel_tex.c312 brw_emit_pipe_control_flush(brw, in intel_texture_barrier()
317 brw_emit_pipe_control_flush(brw, in intel_texture_barrier()
Dbrw_queryobj.c91 brw_emit_pipe_control_flush(brw, in brw_write_timestamp()
122 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in brw_write_depth_count()
Dintel_fbo.c1002 brw_emit_pipe_control_flush(brw, in flush_depth_and_render_caches()
1007 brw_emit_pipe_control_flush(brw, in flush_depth_and_render_caches()
Dhsw_queryobj.c294 brw_emit_pipe_control_flush(brw, in hsw_result_to_gpr0()
Dbrw_draw.c976 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in brw_draw_prims()
Dintel_batchbuffer.c767 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_finish_batch()
DgenX_state_upload.c2157 brw_emit_pipe_control_flush(brw,
4202 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);