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Searched refs:buffer_store_dwordx2 (Results 1 – 25 of 191) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dimm.ll7 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]:
17 ; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]]
27 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
326 ; CHECK: buffer_store_dwordx2 [[REG]]
337 ; CHECK: buffer_store_dwordx2 [[REG]]
348 ; CHECK: buffer_store_dwordx2 [[REG]]
359 ; CHECK: buffer_store_dwordx2 [[REG]]
370 ; CHECK: buffer_store_dwordx2 [[REG]]
381 ; CHECK: buffer_store_dwordx2 [[REG]]
392 ; CHECK: buffer_store_dwordx2 [[REG]]
[all …]
Dbitreverse-inline-immediates.ll18 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
35 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
52 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
69 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
86 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
103 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
120 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
137 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
154 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
Dfcanonicalize.ll171 ; GCN: buffer_store_dwordx2 [[REG]]
181 ; GCN: buffer_store_dwordx2 [[REG]]
191 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
201 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
211 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
221 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
231 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
241 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
251 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
261 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
[all …]
Dglobal_atomics_i64.ll15 ; GCN: buffer_store_dwordx2 [[RET]]
38 ; GCN: buffer_store_dwordx2 [[RET]]
58 ; GCN: buffer_store_dwordx2 [[RET]]
79 ; GCN: buffer_store_dwordx2 [[RET]]
99 ; GCN: buffer_store_dwordx2 [[RET]]
122 ; GCN: buffer_store_dwordx2 [[RET]]
142 ; GCN: buffer_store_dwordx2 [[RET]]
163 ; GCN: buffer_store_dwordx2 [[RET]]
183 ; GCN: buffer_store_dwordx2 [[RET]]
206 ; GCN: buffer_store_dwordx2 [[RET]]
[all …]
Dprivate-element-size.ll17 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
18 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8
19 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16
20 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24
71 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
72 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8
73 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16
74 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24
75 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:32
76 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:40
[all …]
Dand.ll183 ; SI: buffer_store_dwordx2
207 ; SI: buffer_store_dwordx2
225 ; SI: buffer_store_dwordx2
252 ; SI: buffer_store_dwordx2
269 ; SI: buffer_store_dwordx2
270 ; SI: buffer_store_dwordx2
288 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]]
291 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]]
307 ; SI: buffer_store_dwordx2
320 ; SI: buffer_store_dwordx2
[all …]
Dshift-and-i64-ubfe.ll10 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}}
27 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}}
43 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
59 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
75 ; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}}
91 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}}
107 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
123 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
139 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}}
157 ; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}}
[all …]
Dshift-i64-opts.ll10 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
22 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
34 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
45 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
60 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
75 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
86 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
98 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
224 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}}
237 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}}
Dllvm.amdgcn.s.memrealtime.ll9 ; GCN: buffer_store_dwordx2
12 ; GCN: buffer_store_dwordx2
Dsint_to_fp.f64.ll20 ; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
32 ; SI: buffer_store_dwordx2 [[RESULT]]
53 ; SI: buffer_store_dwordx2 [[RESULT]]
Dfma-combine.ll15 ; SI: buffer_store_dwordx2 [[RESULT]]
41 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
42 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
72 ; SI: buffer_store_dwordx2 [[RESULT]]
96 ; SI: buffer_store_dwordx2 [[RESULT]]
122 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
123 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
153 ; SI: buffer_store_dwordx2 [[RESULT]]
179 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
180 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
[all …]
Dfract.f64.ll29 ; GCN: buffer_store_dwordx2 [[FRACT]]
56 ; GCN: buffer_store_dwordx2 [[FRACT]]
84 ; GCN: buffer_store_dwordx2 [[FRACT]]
99 ; VI-UNSAFE: buffer_store_dwordx2 [[FLOOR]]
100 ; VI-UNSAFE: buffer_store_dwordx2 [[FRACT]]
Dllvm.amdgcn.s.memtime.ll10 ; GCN: buffer_store_dwordx2
13 ; GCN: buffer_store_dwordx2
Dreadcyclecounter.ll11 ; GCN: buffer_store_dwordx2
15 ; GCN: buffer_store_dwordx2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dimm.ll7 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]:
17 ; GCN: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]]
27 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
350 ; GCN: buffer_store_dwordx2 [[REG]]
361 ; GCN: buffer_store_dwordx2 [[REG]]
372 ; GCN: buffer_store_dwordx2 [[REG]]
383 ; GCN: buffer_store_dwordx2 [[REG]]
394 ; GCN: buffer_store_dwordx2 [[REG]]
405 ; GCN: buffer_store_dwordx2 [[REG]]
416 ; GCN: buffer_store_dwordx2 [[REG]]
[all …]
Dprivate-element-size.ll17 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:24{{$}}
18 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:16
19 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:32
20 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:40
71 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:32
72 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:40
73 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:48
74 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:56
75 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:88
76 ; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:80
[all …]
Dglobal_atomics_i64.ll18 ; CIVI: buffer_store_dwordx2 [[RET]]
44 ; CIVI: buffer_store_dwordx2 [[RET]]
67 ; CIVI: buffer_store_dwordx2 [[RET]]
91 ; CIVI: buffer_store_dwordx2 [[RET]]
114 ; CIVI: buffer_store_dwordx2 [[RET]]
140 ; CIVI: buffer_store_dwordx2 [[RET]]
163 ; CIVI: buffer_store_dwordx2 [[RET]]
187 ; CIVI: buffer_store_dwordx2 [[RET]]
210 ; CIVI: buffer_store_dwordx2 [[RET]]
236 ; CIVI: buffer_store_dwordx2 [[RET]]
[all …]
Dbitreverse-inline-immediates.ll18 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
35 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
52 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
69 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
86 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
103 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
120 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
137 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
154 ; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
Dand.ll195 ; SI: buffer_store_dwordx2
219 ; SI: buffer_store_dwordx2
237 ; SI: buffer_store_dwordx2
267 ; SI: buffer_store_dwordx2
286 ; SI: buffer_store_dwordx2
287 ; SI: buffer_store_dwordx2
306 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]]
307 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]]
323 ; SI: buffer_store_dwordx2
338 ; SI: buffer_store_dwordx2
[all …]
Dshift-and-i64-ubfe.ll11 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}}
29 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO1]]{{\]}}
45 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
61 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
78 ; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO1]]{{\]}}
95 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO1]]{{\]}}
111 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
127 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
143 ; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}}
162 ; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}}
[all …]
Dfcanonicalize.ll220 ; GCN: buffer_store_dwordx2 [[REG]]
230 ; GCN: buffer_store_dwordx2 [[REG]]
239 ; GCN: buffer_store_dwordx2 [[REG]]
250 ; GCN: buffer_store_dwordx2 [[REG]]
262 ; GCN: buffer_store_dwordx2 [[REG]]
274 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
284 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
294 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
304 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
314 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
[all …]
Dshift-i64-opts.ll10 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
22 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
34 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
45 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
60 ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
75 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
86 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
98 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
224 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}}
237 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}}
Dsint_to_fp.f64.ll20 ; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
32 ; SI: buffer_store_dwordx2 [[RESULT]]
53 ; SI: buffer_store_dwordx2 [[RESULT]]
Dfract.f64.ll29 ; GCN: buffer_store_dwordx2 [[FRACT]]
56 ; GCN: buffer_store_dwordx2 [[FRACT]]
84 ; GCN: buffer_store_dwordx2 [[FRACT]]
99 ; VI-UNSAFE: buffer_store_dwordx2 [[FLOOR]]
100 ; VI-UNSAFE: buffer_store_dwordx2 [[FRACT]]
Dllvm.amdgcn.s.memtime.ll10 ; GCN: buffer_store_dwordx2
13 ; GCN: buffer_store_dwordx2

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