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Searched refs:bus_cnt (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training.c317 u32 bus_cnt; in calc_cs_num() local
324 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in calc_cs_num()
325 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in calc_cs_num()
328 as_bus_params[bus_cnt].cs_bitmask; in calc_cs_num()
339 if_id, bus_cnt, cs_count, in calc_cs_num()
362 u32 bus_cnt = 0, adll_tap = 0; in hws_ddr3_tip_init_controller() local
494 for (bus_cnt = 0; in hws_ddr3_tip_init_controller()
495 bus_cnt < octets_per_if_num; in hws_ddr3_tip_init_controller()
496 bus_cnt++) { in hws_ddr3_tip_init_controller()
497 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in hws_ddr3_tip_init_controller()
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Dddr3_training_leveling.c794 u32 bus_cnt; in ddr3_tip_calc_cs_mask() local
809 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_calc_cs_mask()
810 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_calc_cs_mask()
813 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
815 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
819 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
833 u32 reg_data = 0, temp = 0, iter, if_id, bus_cnt; in ddr3_tip_dynamic_write_leveling() local
952 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_dynamic_write_leveling()
953 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_dynamic_write_leveling()
956 mask_results_pup_reg_map[bus_cnt], in ddr3_tip_dynamic_write_leveling()
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Dddr3_init.c122 u32 bus_cnt, num_of_active_bus = 0; in mv_ddr_get_memory_size_per_cs_in_bits() local
130 for (bus_cnt = 0; bus_cnt < octets_per_if_num - 1/* ignore ecc octet */; bus_cnt++) { in mv_ddr_get_memory_size_per_cs_in_bits()
131 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in mv_ddr_get_memory_size_per_cs_in_bits()
Dddr3_training_ip_engine.c1458 u32 bus_cnt = 0, if_id, dev_num = 0; in ddr3_tip_load_phy_values() local
1464 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_load_phy_values()
1465 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_load_phy_values()
1469 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_load_phy_values()
1472 &phy_reg_bk[if_id][bus_cnt] in ddr3_tip_load_phy_values()
1476 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_load_phy_values()
1479 &phy_reg_bk[if_id][bus_cnt] in ddr3_tip_load_phy_values()
1483 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_load_phy_values()
1486 &phy_reg_bk[if_id][bus_cnt] in ddr3_tip_load_phy_values()
1492 bus_cnt, DDR_PHY_DATA, in ddr3_tip_load_phy_values()
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Dddr3_debug.c851 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; in ddr3_tip_print_adll() local
857 for (bus_cnt = 0; bus_cnt < octets_per_if_num; in ddr3_tip_print_adll()
858 bus_cnt++) { in ddr3_tip_print_adll()
859 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_print_adll()
862 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_print_adll()
866 bus_cnt, DDR_PHY_DATA, 0x2, &data_p2)); in ddr3_tip_print_adll()
869 bus_cnt, DDR_PHY_DATA, 0x3, &ui_data3)); in ddr3_tip_print_adll()
872 if_id, bus_cnt, data_p1, data_p2, in ddr3_tip_print_adll()