Home
last modified time | relevance | path

Searched refs:ccsr (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx5/
Dclock.c235 u32 ccsr = readl(&mxc_ccm->ccsr); in get_lp_apm() local
237 if (ccsr & MXC_CCM_CCSR_LP_APM) in get_lp_apm()
647 u32 ccsr = readl(&mxc_ccm->ccsr); in config_pll_clk() local
653 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL, in config_pll_clk()
654 &mxc_ccm->ccsr); in config_pll_clk()
659 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL, in config_pll_clk()
660 &mxc_ccm->ccsr); in config_pll_clk()
664 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL, in config_pll_clk()
665 &mxc_ccm->ccsr); in config_pll_clk()
670 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL, in config_pll_clk()
[all …]
/external/u-boot/arch/arm/include/asm/arch-armada100/
Dcpu.h45 u32 ccsr; /* 0x00C */ member
/external/u-boot/arch/arm/mach-imx/mx6/
Dclock.c1429 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1431 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1456 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1458 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
/external/u-boot/board/armadeus/apf27/
Dfpga.c198 writel(ACFG_CCSR_VAL, &pll->ccsr); in apf27_fpga_setup()
/external/u-boot/arch/arm/include/asm/arch-vf610/
Dcrm_regs.h17 u32 ccsr; member
/external/u-boot/arch/arm/cpu/armv7/vf610/
Dgeneric.c45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
/external/u-boot/board/freescale/vf610twr/
Dvf610twr.c303 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
/external/u-boot/arch/arm/lib/
Dasm-offsets.c155 DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); in main()
/external/u-boot/board/toradex/colibri_vf/
Dcolibri_vf.c454 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | in clock_init()
/external/u-boot/arch/arm/include/asm/arch-mx27/
Dimx-regs.h125 u32 ccsr; /* Clock Control Status Register */ member
/external/u-boot/arch/arm/include/asm/arch-mx5/
Dimx-regs.h304 u32 ccsr; member
Dcrm_regs.h32 u32 ccsr; member
/external/u-boot/board/phytec/pcm052/
Dpcm052.c497 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dcrm_regs.h25 u32 ccsr; member