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/external/perfetto/ui/src/frontend/
Drecord_page.ts101 const cfg = globals.state.recordConfig; constant
105 checked: cfg.mode === mode,
117 `label${cfg.mode === mode ? '.selected' : ''}`,
136 set: (cfg, val) => cfg.bufferSizeMb = val,
137 get: (cfg) => cfg.bufferSizeMb
146 set: (cfg, val) => cfg.durationMs = val,
147 get: (cfg) => cfg.durationMs
152 cssClass: cfg.mode !== 'LONG_TRACE' ? '.hide' : '',
155 set: (cfg, val) => cfg.maxFileSizeMb = val,
156 get: (cfg) => cfg.maxFileSizeMb
[all …]
/external/syzkaller/pkg/mgrconfig/
Dmgrconfig.go98 cfg, err := LoadPartialData(data)
102 if err := Complete(cfg); err != nil {
105 return cfg, nil
109 cfg, err := LoadPartialFile(filename)
113 if err := Complete(cfg); err != nil {
116 return cfg, nil
120 cfg := defaultValues()
121 if err := config.LoadData(data, cfg); err != nil {
124 return loadPartial(cfg)
128 cfg := defaultValues()
[all …]
/external/yapf/yapftests/
Dstyle_test.py57 def _LooksLikeChromiumStyle(cfg): argument
58 return (cfg['INDENT_WIDTH'] == 2 and
59 cfg['BLANK_LINE_BEFORE_NESTED_CLASS_OR_DEF'])
62 def _LooksLikeGoogleStyle(cfg): argument
63 return (cfg['INDENT_WIDTH'] == 4 and
64 cfg['BLANK_LINE_BEFORE_NESTED_CLASS_OR_DEF'])
67 def _LooksLikePEP8Style(cfg): argument
68 return (cfg['INDENT_WIDTH'] == 4 and
69 not cfg['BLANK_LINE_BEFORE_NESTED_CLASS_OR_DEF'])
72 def _LooksLikeFacebookStyle(cfg): argument
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/external/u-boot/drivers/video/
Dssd2828.c153 static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) in read_hw_register() argument
155 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in read_hw_register()
156 return soft_spi_xfer_24bit_3wire(cfg, 0x730000); in read_hw_register()
162 static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, in write_hw_register() argument
165 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in write_hw_register()
166 soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); in write_hw_register()
172 static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) in send_mipi_dcs_command() argument
175 write_hw_register(cfg, SSD2828_PSCR1, 1); in send_mipi_dcs_command()
177 write_hw_register(cfg, SSD2828_PDR, cmdnum); in send_mipi_dcs_command()
183 static void ssd2828_reset(const struct ssd2828_config *cfg) in ssd2828_reset() argument
[all …]
/external/skqp/src/sksl/
DSkSLCFGGenerator.cpp294 void CFGGenerator::addExpression(CFG& cfg, std::unique_ptr<Expression>* e, bool constantPropagate) { in addExpression() argument
305 this->addExpression(cfg, &b->fLeft, constantPropagate); in addExpression()
306 BlockId start = cfg.fCurrent; in addExpression()
307 cfg.newBlock(); in addExpression()
308 this->addExpression(cfg, &b->fRight, constantPropagate); in addExpression()
309 cfg.newBlock(); in addExpression()
310 cfg.addExit(start, cfg.fCurrent); in addExpression()
311 cfg.fBlocks[cfg.fCurrent].fNodes.push_back({ in addExpression()
320 this->addExpression(cfg, &b->fRight, constantPropagate); in addExpression()
321 this->addLValue(cfg, &b->fLeft); in addExpression()
[all …]
/external/skia/src/sksl/
DSkSLCFGGenerator.cpp294 void CFGGenerator::addExpression(CFG& cfg, std::unique_ptr<Expression>* e, bool constantPropagate) { in addExpression() argument
305 this->addExpression(cfg, &b->fLeft, constantPropagate); in addExpression()
306 BlockId start = cfg.fCurrent; in addExpression()
307 cfg.newBlock(); in addExpression()
308 this->addExpression(cfg, &b->fRight, constantPropagate); in addExpression()
309 cfg.newBlock(); in addExpression()
310 cfg.addExit(start, cfg.fCurrent); in addExpression()
311 cfg.fBlocks[cfg.fCurrent].fNodes.push_back({ in addExpression()
320 this->addExpression(cfg, &b->fRight, constantPropagate); in addExpression()
321 this->addLValue(cfg, &b->fLeft); in addExpression()
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/external/iptables/extensions/
Dlibxt_hashlimit.c104 XTOPT_POINTER(s, cfg.burst)},
107 XTOPT_POINTER(s, cfg.size)},
110 XTOPT_POINTER(s, cfg.max)},
113 XTOPT_POINTER(s, cfg.gc_interval)},
116 XTOPT_POINTER(s, cfg.expire)},
138 XTOPT_POINTER(s, cfg.size)},
141 XTOPT_POINTER(s, cfg.max)},
144 XTOPT_POINTER(s, cfg.gc_interval)},
147 XTOPT_POINTER(s, cfg.expire)},
168 XTOPT_POINTER(s, cfg.size)},
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/external/libvpx/libvpx/examples/
Dvpx_temporal_svc_encoder.c94 vpx_codec_enc_cfg_t *cfg) { in set_rate_control_metrics() argument
98 const double framerate = cfg->g_timebase.den / cfg->g_timebase.num; in set_rate_control_metrics()
99 rc->layer_framerate[0] = framerate / cfg->ts_rate_decimator[0]; in set_rate_control_metrics()
102 for (i = 0; i < cfg->ts_number_layers; ++i) { in set_rate_control_metrics()
104 rc->layer_framerate[i] = framerate / cfg->ts_rate_decimator[i]; in set_rate_control_metrics()
124 vpx_codec_enc_cfg_t *cfg, in printout_rate_control_summary() argument
131 cfg->ts_number_layers); in printout_rate_control_summary()
132 for (i = 0; i < cfg->ts_number_layers; ++i) { in printout_rate_control_summary()
172 static void set_roi_map(const char *enc_name, vpx_codec_enc_cfg_t *cfg, in set_roi_map() argument
187 roi->rows = (cfg->g_h + block_size - 1) / block_size; in set_roi_map()
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Dvp8_multi_resolution_encoder.c124 static void write_ivf_file_header(FILE *outfile, const vpx_codec_enc_cfg_t *cfg, in write_ivf_file_header() argument
128 if (cfg->g_pass != VPX_RC_ONE_PASS && cfg->g_pass != VPX_RC_LAST_PASS) return; in write_ivf_file_header()
136 mem_put_le16(header + 12, cfg->g_w); /* width */ in write_ivf_file_header()
137 mem_put_le16(header + 14, cfg->g_h); /* height */ in write_ivf_file_header()
138 mem_put_le32(header + 16, cfg->g_timebase.den); /* rate */ in write_ivf_file_header()
139 mem_put_le32(header + 20, cfg->g_timebase.num); /* scale */ in write_ivf_file_header()
167 vpx_codec_enc_cfg_t *cfg, int bitrate, in set_temporal_layer_pattern() argument
173 cfg->ts_number_layers = 1; in set_temporal_layer_pattern()
174 cfg->ts_periodicity = 1; in set_temporal_layer_pattern()
175 cfg->ts_rate_decimator[0] = 1; in set_temporal_layer_pattern()
[all …]
/external/libaom/libaom/av1/encoder/
Dav1_fwd_txfm2d.c42 const TXFM_2D_FLIP_CFG *cfg, int bd) { in av1_gen_fwd_stage_range() argument
44 const int8_t *shift = cfg->shift; in av1_gen_fwd_stage_range()
46 for (int i = 0; i < cfg->stage_num_col && i < MAX_TXFM_STAGE_NUM; ++i) { in av1_gen_fwd_stage_range()
47 stage_range_col[i] = cfg->stage_range_col[i] + shift[0] + bd + 1; in av1_gen_fwd_stage_range()
51 for (int i = 0; i < cfg->stage_num_row && i < MAX_TXFM_STAGE_NUM; ++i) { in av1_gen_fwd_stage_range()
52 stage_range_row[i] = cfg->stage_range_row[i] + shift[0] + shift[1] + bd + 1; in av1_gen_fwd_stage_range()
57 const int stride, const TXFM_2D_FLIP_CFG *cfg, in fwd_txfm2d_c() argument
66 const int txfm_size_col = tx_size_wide[cfg->tx_size]; in fwd_txfm2d_c()
67 const int txfm_size_row = tx_size_high[cfg->tx_size]; in fwd_txfm2d_c()
69 const int8_t *shift = cfg->shift; in fwd_txfm2d_c()
[all …]
/external/libvpx/libvpx/test/
Dencode_api_test.cc33 vpx_codec_enc_cfg_t cfg; in TEST() local
45 vpx_codec_enc_config_default(NULL, &cfg, 0)); in TEST()
55 vpx_codec_enc_config_default(kCodecs[i], &cfg, 1)); in TEST()
57 EXPECT_EQ(VPX_CODEC_OK, vpx_codec_enc_config_default(kCodecs[i], &cfg, 0)); in TEST()
58 EXPECT_EQ(VPX_CODEC_OK, vpx_codec_enc_init(&enc, kCodecs[i], &cfg, 0)); in TEST()
89 vpx_codec_enc_cfg_t cfg; in TEST() local
92 vpx_codec_enc_config_default(vpx_codec_vp8_cx(), &cfg, 0); in TEST()
94 cfg.g_w = width; in TEST()
95 cfg.g_h = height; in TEST()
99 vpx_codec_enc_init(&enc, vpx_codec_vp8_cx(), &cfg, 0); in TEST()
[all …]
Dcodec_factory.h37 virtual Decoder *CreateDecoder(vpx_codec_dec_cfg_t cfg) const = 0;
39 virtual Decoder *CreateDecoder(vpx_codec_dec_cfg_t cfg,
42 virtual Encoder *CreateEncoder(vpx_codec_enc_cfg_t cfg,
47 virtual vpx_codec_err_t DefaultEncoderConfig(vpx_codec_enc_cfg_t *cfg,
81 explicit VP8Decoder(vpx_codec_dec_cfg_t cfg) : Decoder(cfg) {} in VP8Decoder() argument
83 VP8Decoder(vpx_codec_dec_cfg_t cfg, const vpx_codec_flags_t flag) in VP8Decoder() argument
84 : Decoder(cfg, flag) {} in VP8Decoder()
98 VP8Encoder(vpx_codec_enc_cfg_t cfg, unsigned long deadline, in VP8Encoder() argument
100 : Encoder(cfg, deadline, init_flags, stats) {} in VP8Encoder()
116 virtual Decoder *CreateDecoder(vpx_codec_dec_cfg_t cfg) const { in CreateDecoder() argument
[all …]
/external/syzkaller/vendor/google.golang.org/grpc/credentials/
Dcredentials_util_go17.go33 func cloneTLSConfig(cfg *tls.Config) *tls.Config {
34 if cfg == nil {
38 Rand: cfg.Rand,
39 Time: cfg.Time,
40 Certificates: cfg.Certificates,
41 NameToCertificate: cfg.NameToCertificate,
42 GetCertificate: cfg.GetCertificate,
43 RootCAs: cfg.RootCAs,
44 NextProtos: cfg.NextProtos,
45 ServerName: cfg.ServerName,
[all …]
Dcredentials_util_pre_go17.go32 func cloneTLSConfig(cfg *tls.Config) *tls.Config {
33 if cfg == nil {
37 Rand: cfg.Rand,
38 Time: cfg.Time,
39 Certificates: cfg.Certificates,
40 NameToCertificate: cfg.NameToCertificate,
41 GetCertificate: cfg.GetCertificate,
42 RootCAs: cfg.RootCAs,
43 NextProtos: cfg.NextProtos,
44 ServerName: cfg.ServerName,
[all …]
/external/u-boot/drivers/video/exynos/
Dexynos_fb.c105 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
108 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
112 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
116 writel(cfg, &reg->dualrgb); in exynos_fimd_set_dualrgb()
123 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
126 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
128 writel(cfg, &reg->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
135 unsigned int cfg = 0; in exynos_fimd_set_par() local
138 cfg = readl((unsigned int)&reg->wincon0 + in exynos_fimd_set_par()
141 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen7_l3_state.c71 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) in setup_l3_config() argument
74 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL]; in setup_l3_config()
75 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] || in setup_l3_config()
76 cfg->n[GEN_L3P_ALL]; in setup_l3_config()
77 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] || in setup_l3_config()
78 cfg->n[GEN_L3P_ALL]; in setup_l3_config()
79 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] || in setup_l3_config()
80 cfg->n[GEN_L3P_ALL]; in setup_l3_config()
81 const bool has_slm = cfg->n[GEN_L3P_SLM]; in setup_l3_config()
122 assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]); in setup_l3_config()
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/external/u-boot/drivers/ddr/altera/
Dsdram_gen5.c40 static int get_errata_rows(const struct socfpga_sdram_config *cfg) in get_errata_rows() argument
46 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in get_errata_rows()
49 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> in get_errata_rows()
52 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> in get_errata_rows()
55 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> in get_errata_rows()
266 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) in sdr_get_ctrlcfg() argument
269 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in sdr_get_ctrlcfg()
272 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> in sdr_get_ctrlcfg()
275 u32 ctrl_cfg = cfg->ctrl_cfg; in sdr_get_ctrlcfg()
304 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) in sdr_get_addr_rw() argument
[all …]
/external/libvpx/libvpx/vp8/
Dvp8_cx_iface.c76 vpx_codec_enc_cfg_t cfg; member
131 const vpx_codec_enc_cfg_t *cfg, in validate_config() argument
134 RANGE_CHECK(cfg, g_w, 1, 16383); /* 14 bits available */ in validate_config()
135 RANGE_CHECK(cfg, g_h, 1, 16383); /* 14 bits available */ in validate_config()
136 RANGE_CHECK(cfg, g_timebase.den, 1, 1000000000); in validate_config()
137 RANGE_CHECK(cfg, g_timebase.num, 1, 1000000000); in validate_config()
138 RANGE_CHECK_HI(cfg, g_profile, 3); in validate_config()
139 RANGE_CHECK_HI(cfg, rc_max_quantizer, 63); in validate_config()
140 RANGE_CHECK_HI(cfg, rc_min_quantizer, cfg->rc_max_quantizer); in validate_config()
141 RANGE_CHECK_HI(cfg, g_threads, 64); in validate_config()
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/external/libnl/lib/route/cls/ematch/
Dtext.c27 struct tcf_em_text cfg; member
35 t->cfg.from_offset = offset; in rtnl_ematch_text_set_from()
36 t->cfg.from_layer = layer; in rtnl_ematch_text_set_from()
41 return ((struct text_data *) rtnl_ematch_data(e))->cfg.from_offset; in rtnl_ematch_text_get_from_offset()
46 return ((struct text_data *) rtnl_ematch_data(e))->cfg.from_layer; in rtnl_ematch_text_get_from_layer()
53 t->cfg.to_offset = offset; in rtnl_ematch_text_set_to()
54 t->cfg.to_layer = layer; in rtnl_ematch_text_set_to()
59 return ((struct text_data *) rtnl_ematch_data(e))->cfg.to_offset; in rtnl_ematch_text_get_to_offset()
64 return ((struct text_data *) rtnl_ematch_data(e))->cfg.to_layer; in rtnl_ematch_text_get_to_layer()
76 t->cfg.pattern_len = len; in rtnl_ematch_text_set_pattern()
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/external/syzkaller/pkg/instance/
Dinstance.go30 cfg *mgrconfig.Config member
33 func NewEnv(cfg *mgrconfig.Config) (*Env, error) {
34 switch cfg.Type {
39 if cfg.Workdir == "" {
42 if cfg.KernelSrc == "" {
45 if cfg.Syzkaller == "" {
48 if err := osutil.MkdirAll(cfg.Workdir); err != nil {
52 cfg: cfg,
58 cfg := env.cfg
59 srcIndex := strings.LastIndex(cfg.Syzkaller, "/src/")
[all …]
/external/syzkaller/pkg/bisect/
Dbisect.go53 cfg *Config member
66 func Run(cfg *Config) (*vcs.Commit, error) {
67 repo, err := vcs.NewRepo(cfg.Manager.TargetOS, cfg.Manager.Type, cfg.Manager.KernelSrc)
72 cfg: cfg,
75 if cfg.Fix {
76 env.log("searching for fixing commit since %v", cfg.Kernel.Commit)
78 env.log("searching for guilty commit starting from %v", cfg.Kernel.Commit)
93 if cfg.Fix {
102 cfg := env.cfg
104 if env.inst, err = instance.NewEnv(&cfg.Manager); err != nil {
[all …]
/external/syzkaller/pkg/ifuzz/
Difuzz.go54 generator func(cfg *Config, r *rand.Rand) []byte // for pseudo instructions
109 func ModeInsns(cfg *Config) []*Insn {
111 if cfg.Mode < 0 || cfg.Mode >= ModeLast {
115 insns = append(insns, modeInsns[cfg.Mode][typeUser]...)
116 if cfg.Priv {
117 insns = append(insns, modeInsns[cfg.Mode][typePriv]...)
118 if cfg.Exec {
119 insns = append(insns, modeInsns[cfg.Mode][typeExec]...)
125 func Generate(cfg *Config, r *rand.Rand) []byte {
128 for i := 0; i < cfg.Len; i++ {
[all …]
/external/u-boot/include/linux/
Dkconfig.h20 #define config_enabled(cfg) _config_enabled(cfg) argument
59 #define config_val(cfg) _config_val(_IS_TPL, cfg) argument
60 #define _config_val(x, cfg) __config_val(x, cfg) argument
61 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) argument
62 #define ___config_val(arg1_or_junk, cfg) \ argument
63 ____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
66 #define config_val(cfg) _config_val(_IS_SPL, cfg) argument
67 #define _config_val(x, cfg) __config_val(x, cfg) argument
68 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) argument
69 #define ___config_val(arg1_or_junk, cfg) \ argument
[all …]
/external/u-boot/drivers/pinctrl/renesas/
Dsh_pfc.h356 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
357 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
360 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
361 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
362 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
363 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
364 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
367 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
368 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
369 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
[all …]
/external/u-boot/drivers/power/
Daxp818.c32 u8 cfg = axp818_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
38 ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg); in axp_set_dcdc1()
49 u8 cfg; in axp_set_dcdc2() local
52 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); in axp_set_dcdc2()
54 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); in axp_set_dcdc2()
60 ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg); in axp_set_dcdc2()
71 u8 cfg; in axp_set_dcdc3() local
74 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); in axp_set_dcdc3()
76 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); in axp_set_dcdc3()
82 ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg); in axp_set_dcdc3()
[all …]

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