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Searched refs:chip_class (Results 1 – 25 of 90) sorted by relevance

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/external/mesa3d/src/amd/common/
Dac_debug.c62 enum chip_class chip_class; member
117 void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, in ac_dump_reg() argument
122 if (chip_class >= GFX9) in ac_dump_reg()
213 ac_dump_reg(f, ib->chip_class, reg + i*4, ac_ib_get(ib), ~0); in ac_parse_set_reg_packet()
261 ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); in ac_parse_packet3()
262 ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); in ac_parse_packet3()
263 ac_dump_reg(f, ib->chip_class, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0); in ac_parse_packet3()
264 ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0); in ac_parse_packet3()
265 ac_dump_reg(f, ib->chip_class, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0); in ac_parse_packet3()
269 if (ib->chip_class >= CIK) { in ac_parse_packet3()
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Dac_debug.h55 void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
58 unsigned trace_id_count, enum chip_class chip_class,
61 unsigned trace_id_count, const char *name, enum chip_class chip_class,
64 bool ac_vm_fault_occured(enum chip_class chip_class,
Dac_shader_util.c90 ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class) in ac_vgt_gs_mode() argument
107 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) | in ac_vgt_gs_mode()
109 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0); in ac_vgt_gs_mode()
172 if (ctx->chip_class == SI && in ac_export_mrt_z()
Dac_gpu_info.c252 info->chip_class = GFX9; in ac_query_gpu_info()
254 info->chip_class = VI; in ac_query_gpu_info()
256 info->chip_class = CIK; in ac_query_gpu_info()
258 info->chip_class = SI; in ac_query_gpu_info()
298 if (info->chip_class == GFX9) { in ac_query_gpu_info()
332 if (info->chip_class == SI) in ac_query_gpu_info()
383 printf("chip_class = %i\n", info->chip_class); in ac_print_gpu_info()
Dac_shader_util.h41 ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class);
/external/mesa3d/src/amd/vulkan/
Dradv_debug.c75 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, in radv_init_trace()
104 ac_dump_reg(f, device->physical_device->rad_info.chip_class, in radv_dump_mmapped_reg()
132 if (info->chip_class <= VI) { in radv_dump_debug_registers()
182 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, in radv_dump_buffer_descriptor() argument
187 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, in radv_dump_buffer_descriptor()
192 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, in radv_dump_image_descriptor() argument
197 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4, in radv_dump_image_descriptor()
202 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4, in radv_dump_image_descriptor()
207 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, in radv_dump_sampler_descriptor() argument
212 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, in radv_dump_sampler_descriptor()
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Dsi_cmd_buffer.c149 if (physical_device->rad_info.chip_class < CIK) in si_write_harvested_raster_configs()
159 if (physical_device->rad_info.chip_class >= CIK) in si_write_harvested_raster_configs()
164 if (physical_device->rad_info.chip_class < CIK) in si_write_harvested_raster_configs()
191 if (physical_device->rad_info.chip_class >= CIK) { in si_emit_compute()
206 if (physical_device->rad_info.chip_class <= SI) { in si_emit_compute()
322 if (physical_device->rad_info.chip_class >= CIK) in si_set_raster_config()
340 physical_device->rad_info.chip_class == SI); in si_emit_config()
351 if (physical_device->rad_info.chip_class <= VI) in si_emit_config()
359 if (physical_device->rad_info.chip_class <= VI) { in si_emit_config()
373 if (physical_device->rad_info.chip_class < CIK) in si_emit_config()
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Dradv_image.c50 && device->physical_device->rad_info.chip_class <= VI) { in radv_choose_tiling()
117 device->physical_device->rad_info.chip_class >= VI && in radv_init_surface()
121 (device->physical_device->rad_info.chip_class >= GFX9 && in radv_init_surface()
157 device->physical_device->rad_info.chip_class < VI || in radv_init_surface()
224 if (device->physical_device->rad_info.chip_class != VI && stride) { in radv_make_buffer_descriptor()
247 enum chip_class chip_class = device->physical_device->rad_info.chip_class; in si_set_mutable_tex_desc_fields() local
249 if (chip_class >= GFX9) { in si_set_mutable_tex_desc_fields()
258 if (chip_class >= GFX9 || in si_set_mutable_tex_desc_fields()
264 if (chip_class >= VI) { in si_set_mutable_tex_desc_fields()
269 if (chip_class <= VI) in si_set_mutable_tex_desc_fields()
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Dradv_shader.c125 device->rad_info.chip_class <= VI; in radv_lower_indirect_derefs()
394 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_fill_shader_variant()
422 if (device->physical_device->rad_info.chip_class >= GFX9 && in radv_fill_shader_variant()
451 } else if (device->physical_device->rad_info.chip_class >= GFX9 && in radv_fill_shader_variant()
484 options->chip_class = device->physical_device->rad_info.chip_class; in shader_variant_create()
605 if (device->physical_device->rad_info.chip_class >= VI) in get_total_sgprs()
617 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; in generate_shader_stats()
717 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; in radv_GetShaderInfoAMD()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.c107 bool has_primid_instancing_bug = sctx->b.chip_class == SI && in si_emit_derived_tess_state()
120 if (sctx->b.chip_class >= GFX9) { in si_emit_derived_tess_state()
198 if (sctx->b.chip_class == SI) { in si_emit_derived_tess_state()
246 if (sctx->b.chip_class >= CIK) { in si_emit_derived_tess_state()
259 if (sctx->b.chip_class >= GFX9) { in si_emit_derived_tess_state()
280 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII) in si_emit_derived_tess_state()
304 if (sctx->b.chip_class >= CIK) in si_emit_derived_tess_state()
353 if (sscreen->info.chip_class <= VI) in si_get_init_multi_vgt_param()
376 if (sscreen->info.chip_class >= CIK) { in si_get_init_multi_vgt_param()
409 if (sscreen->info.chip_class <= VI && in si_get_init_multi_vgt_param()
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Dsi_pipe.c212 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) | in si_create_llvm_target_machine()
213 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) | in si_create_llvm_target_machine()
321 if (sctx->b.chip_class >= CIK) in si_create_context()
337 if (sctx->b.chip_class >= GFX9) { in si_create_context()
359 if (sctx->b.chip_class == CIK) { in si_create_context()
527 if (sscreen->info.chip_class >= GFX9) in si_init_gs_info()
572 sscreen->info.chip_class = GFX9; in si_handle_env_var_force_family()
574 sscreen->info.chip_class = VI; in si_handle_env_var_force_family()
576 sscreen->info.chip_class = CIK; in si_handle_env_var_force_family()
578 sscreen->info.chip_class = SI; in si_handle_env_var_force_family()
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Dsi_debug.c232 ac_dump_reg(f, sctx->b.chip_class, offset, value, ~0); in si_dump_mmapped_reg()
258 if (sctx->b.chip_class <= VI) { in si_dump_debug_registers()
293 const char *name, enum chip_class chip_class) in si_parse_current_ib() argument
309 chip_class, NULL, NULL); in si_parse_current_ib()
326 trace_id_count, chip_class, NULL, NULL); in si_parse_current_ib()
354 NULL, 0, "IB2: Init config", ctx->b.chip_class, in si_log_chunk_type_cs_print()
360 NULL, 0, "IB2: Init GS rings", ctx->b.chip_class, in si_log_chunk_type_cs_print()
367 &last_trace_id, map ? 1 : 0, "IB", ctx->b.chip_class, in si_log_chunk_type_cs_print()
372 "IB", ctx->b.chip_class); in si_log_chunk_type_cs_print()
567 enum chip_class chip_class; member
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Dsi_cp_dma.c48 unsigned max = sctx->b.chip_class >= GFX9 ? in cp_dma_max_byte_count()
71 if (sctx->b.chip_class >= GFX9) in si_emit_cp_dma()
80 if (sctx->b.chip_class >= GFX9) in si_emit_cp_dma()
90 if (sctx->b.chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) && in si_emit_cp_dma()
101 if (sctx->b.chip_class >= CIK) { in si_emit_cp_dma()
140 (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0); in get_flush_flags()
148 if ((sctx->b.chip_class >= GFX9 && coher == R600_COHERENCY_CB_META) || in get_tc_l2_flag()
149 (sctx->b.chip_class >= CIK && coher == R600_COHERENCY_SHADER)) in get_tc_l2_flag()
500 assert(sctx->b.chip_class >= CIK); in cik_prefetch_TC_L2_async()
528 if (sctx->b.chip_class >= GFX9) { in cik_emit_prefetch_L2()
Dcik_sdma.c57 radeon_emit(cs, ctx->b.chip_class >= GFX9 ? csize - 1 : csize); in cik_sdma_copy_buffer()
104 radeon_emit(cs, sctx->b.chip_class >= GFX9 ? csize - 1 : csize); in cik_sdma_clear_buffer()
224 (sctx->b.chip_class != CIK || in cik_sdma_copy_texture()
250 if (sctx->b.chip_class == CIK) { in cik_sdma_copy_texture()
307 if (sctx->b.chip_class == CIK && in cik_sdma_copy_texture()
414 if (sctx->b.chip_class == CIK) { in cik_sdma_copy_texture()
439 (sctx->b.chip_class >= VI && in cik_sdma_copy_texture()
478 (sctx->b.chip_class != CIK || in cik_sdma_copy_texture()
508 if (sctx->b.chip_class == CIK) { in cik_sdma_copy_texture()
544 if ((sctx->b.chip_class == CIK || sctx->b.chip_class == VI) && in cik_sdma_copy()
Dsi_state.c123 if (sctx->b.chip_class >= VI) { in si_emit_cb_render_state()
128 bool oc_disable = (sctx->b.chip_class == VI || in si_emit_cb_render_state()
129 sctx->b.chip_class == GFX9) && in si_emit_cb_render_state()
933 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9)); in si_create_rs_state()
1405 if (sctx->b.chip_class >= CIK) { in si_emit_db_render_state()
1419 if (sctx->b.chip_class >= CIK) { in si_emit_db_render_state()
1435 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) { in si_emit_db_render_state()
1678 sscreen->info.chip_class >= GFX9)) { in si_translate_texformat()
1933 sscreen->info.chip_class >= GFX9 && in si_tex_dim()
2445 if (sctx->b.chip_class == SI) { in si_initialize_color_surface()
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Dsi_compute.c287 if (sctx->b.chip_class >= CIK) { in si_initialize_compute()
302 if (sctx->b.chip_class <= SI) { in si_initialize_compute()
313 if (sctx->b.chip_class >= CIK) { in si_initialize_compute()
401 if (sctx->b.chip_class <= SI) { in si_switch_compute_shader()
436 if (sctx->b.chip_class >= CIK) { in si_switch_compute_shader()
496 if (sctx->b.chip_class >= GFX9) { in setup_scratch_rsrc_user_sgprs()
501 if (sctx->b.chip_class < VI) { in setup_scratch_rsrc_user_sgprs()
730 if (sctx->b.chip_class >= CIK) { in si_emit_dispatch_packets()
755 S_00B800_ORDER_MODE(sctx->b.chip_class >= CIK); in si_emit_dispatch_packets()
800 (sctx->b.chip_class == SI || in si_launch_grid()
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/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c207 ws->info.chip_class = R300; in do_winsys_init()
218 ws->info.chip_class = R400; in do_winsys_init()
226 ws->info.chip_class = R500; in do_winsys_init()
236 ws->info.chip_class = R600; in do_winsys_init()
242 ws->info.chip_class = R700; in do_winsys_init()
255 ws->info.chip_class = EVERGREEN; in do_winsys_init()
259 ws->info.chip_class = CAYMAN; in do_winsys_init()
266 ws->info.chip_class = SI; in do_winsys_init()
273 ws->info.chip_class = CIK; in do_winsys_init()
304 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { in do_winsys_init()
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/external/mesa3d/src/gallium/drivers/r600/
Dr600_hw_context.c73 if (ctx->b.chip_class == R600) { in r600_need_cs_space()
134 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
140 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
155 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { in r600_flush_emit()
181 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
191 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
203 if (rctx->b.chip_class >= EVERGREEN) in r600_flush_emit()
210 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
280 if (ctx->b.chip_class == R600) { in r600_context_gfx_flush()
351 if (ctx->b.chip_class >= EVERGREEN) { in r600_begin_new_cs()
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Dr600_isa.h693 r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) { in r600_isa_alu_opcode() argument
694 int opc = r600_isa_alu(op)->opcode[chip_class >> 1]; in r600_isa_alu_opcode()
700 r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) { in r600_isa_alu_slots() argument
701 unsigned slots = r600_isa_alu(op)->slots[chip_class]; in r600_isa_alu_slots()
707 r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) { in r600_isa_fetch_opcode() argument
708 int opc = r600_isa_fetch(op)->opcode[chip_class]; in r600_isa_fetch_opcode()
714 r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) { in r600_isa_cf_opcode() argument
715 int opc = r600_isa_cf(op)->opcode[chip_class]; in r600_isa_cf_opcode()
Deg_debug.c144 int trace_id, enum chip_class chip_class, in ac_parse_packet3() argument
286 const char *name, enum chip_class chip_class, in eg_parse_ib() argument
297 chip_class, addr_callback, in eg_parse_ib()
344 last_trace_id, "IB", rctx->b.chip_class, in eg_dump_last_ib()
Dr600_asm.c140 enum chip_class chip_class, in r600_bytecode_init() argument
148 if ((chip_class == R600) && in r600_bytecode_init()
158 bc->chip_class = chip_class; in r600_bytecode_init()
321 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in assign_alu_units()
409 if (bc->chip_class >= R700) { in reserve_cfile()
530 boolean scalar_only = bc->chip_class == CAYMAN ? false : true; in check_and_set_bank_swizzle()
531 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in check_and_set_bank_swizzle()
609 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in replace_gpr_with_pv_ps()
645 if (bc->chip_class < CAYMAN) { in replace_gpr_with_pv_ps()
760 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in merge_inst_groups()
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Deg_asm.c78 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
98 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
116 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
133 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
144 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
182 assert(bc->chip_class >= EVERGREEN); in egcm_load_index_reg()
191 if (bc->chip_class == CAYMAN) in egcm_load_index_reg()
201 if (bc->chip_class == EVERGREEN) { in egcm_load_index_reg()
Dr600_asm.h239 enum chip_class chip_class; member
275 enum chip_class chip_class,
Dr600_pipe.c160 switch (rctx->b.chip_class) { in r600_create_context()
166 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx) in r600_create_context()
196 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class); in r600_create_context()
311 return rscreen->b.chip_class > R700; in r600_get_param()
510 return rscreen->b.chip_class >= R700; in r600_get_param()
694 if (rscreen->b.info.chip_class >= EVERGREEN) { in r600_screen_create()
715 switch (rscreen->b.chip_class) { in r600_screen_create()
736 switch (rscreen->b.chip_class) { in r600_screen_create()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_pipe_common.c62 if (ctx->chip_class >= GFX9) { in si_gfx_write_event_eop()
70 if (ctx->chip_class == GFX9 && in si_gfx_write_event_eop()
96 if (ctx->chip_class == CIK || in si_gfx_write_event_eop()
97 ctx->chip_class == VI) { in si_gfx_write_event_eop()
134 if (screen->info.chip_class == CIK || in si_gfx_write_fence_dwords()
135 screen->info.chip_class == VI) in si_gfx_write_fence_dwords()
163 if (rctx->chip_class >= CIK) in r600_dma_emit_wait_idle()
415 rctx->chip_class = sscreen->info.chip_class; in si_common_context_init()
431 if (rctx->chip_class == CIK || in si_common_context_init()
432 rctx->chip_class == VI || in si_common_context_init()
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