| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_vce_50.c | 75 signed luma_offset, chroma_offset, bs_offset; in encode() local
171 si_vce_frame_offset(enc, l0, &luma_offset, &chroma_offset); in encode()
176 RVCE_CS(chroma_offset); // chromaOffset in encode()
197 si_vce_frame_offset(enc, l1, &luma_offset, &chroma_offset); in encode()
202 RVCE_CS(chroma_offset); // chromaOffset in encode()
211 si_vce_frame_offset(enc, si_current_slot(enc), &luma_offset, &chroma_offset); in encode()
213 RVCE_CS(chroma_offset); // encReconstructedChromaOffset in encode()
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| D | radeon_vce_40_2_2.c | 294 signed luma_offset, chroma_offset; in encode() local
361 si_vce_frame_offset(enc, l0, &luma_offset, &chroma_offset); in encode()
366 RVCE_CS(chroma_offset); // chromaOffset in encode()
387 si_vce_frame_offset(enc, l1, &luma_offset, &chroma_offset); in encode()
392 RVCE_CS(chroma_offset); // chromaOffset in encode()
401 si_vce_frame_offset(enc, si_current_slot(enc), &luma_offset, &chroma_offset); in encode()
403 RVCE_CS(chroma_offset); // encReconstructedChromaOffset in encode()
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| D | radeon_vce_52.c | 204 signed luma_offset, chroma_offset, bs_offset; in encode() local
323 si_vce_frame_offset(enc, l0, &luma_offset, &chroma_offset); in encode()
328 RVCE_CS(chroma_offset); in encode()
360 si_vce_frame_offset(enc, l1, &luma_offset, &chroma_offset); in encode()
365 RVCE_CS(chroma_offset); in encode()
379 si_vce_frame_offset(enc, si_current_slot(enc), &luma_offset, &chroma_offset); in encode()
381 RVCE_CS(chroma_offset); in encode()
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| D | radeon_vce.c | 220 signed *luma_offset, signed *chroma_offset) in si_vce_frame_offset() argument
235 *chroma_offset = *luma_offset + pitch * vpitch; in si_vce_frame_offset()
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| D | radeon_vcn_enc.h | 289 uint32_t chroma_offset; member
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| D | radeon_vce.h | 418 signed *luma_offset, signed *chroma_offset);
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| /external/libdrm/tests/amdgpu/ |
| D | vce_tests.c | 313 uint64_t luma_offset, chroma_offset; in amdgpu_cs_vce_encode_idr() local
319 chroma_offset = luma_offset + luma_size; in amdgpu_cs_vce_encode_idr()
346 ib_cpu[len + 11] = chroma_offset >> 32; in amdgpu_cs_vce_encode_idr()
347 ib_cpu[len + 12] = chroma_offset; in amdgpu_cs_vce_encode_idr()
362 uint64_t luma_offset, chroma_offset; in amdgpu_cs_vce_encode_p() local
369 chroma_offset = luma_offset + luma_size; in amdgpu_cs_vce_encode_p()
399 ib_cpu[len + 11] = chroma_offset >> 32; in amdgpu_cs_vce_encode_p()
400 ib_cpu[len + 12] = chroma_offset; in amdgpu_cs_vce_encode_p()
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| D | uvd_enc_tests.c | 331 uint64_t luma_offset, chroma_offset; in amdgpu_cs_uvd_enc_encode() local
434 chroma_offset = luma_offset + luma_size; in amdgpu_cs_uvd_enc_encode()
441 ib_cpu[len++] = chroma_offset >> 32; in amdgpu_cs_uvd_enc_encode()
442 ib_cpu[len++] = chroma_offset; in amdgpu_cs_uvd_enc_encode()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_vce.c | 226 signed *luma_offset, signed *chroma_offset) in rvce_frame_offset() argument
235 *chroma_offset = *luma_offset + pitch * vpitch; in rvce_frame_offset()
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| D | radeon_vce.h | 424 signed *luma_offset, signed *chroma_offset);
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| /external/v4l2_codec2/vda/ |
| D | h264_parser.h | 231 int chroma_offset[32][2]; member
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| D | h264_parser.cc | 1188 READ_SE_OR_RETURN(&w_facts->chroma_offset[i][j]); in ParseWeightingFactors()
1189 IN_RANGE_OR_RETURN(w_facts->chroma_offset[i][j], -128, 127); in ParseWeightingFactors()
1194 w_facts->chroma_offset[i][j] = 0; in ParseWeightingFactors()
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| /external/libhevc/encoder/ |
| D | hme_interface.h | 214 S32 chroma_offset; member
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| D | ihevce_me_pass.c | 764 ps_ref_info->chroma_offset = 0; in ihevc_me_update_ref_desc()
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