Home
last modified time | relevance | path

Searched refs:cl_val (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_topology.c129 cas_latency_table[speed_bin_index].cl_val[freq]; in mv_ddr_topology_map_update()
133 cas_write_latency_table[speed_bin_index].cl_val[freq]; in mv_ddr_topology_map_update()
Dddr3_training_leveling.c65 u32 bus_num, if_id, cl_val; in ddr3_tip_dynamic_read_leveling() local
146 cl_val = in ddr3_tip_dynamic_read_leveling()
147 cas_latency_table[speed_bin_index].cl_val[freq]; in ddr3_tip_dynamic_read_leveling()
148 data = (cl_val << 17) | (0x3 << 25); in ddr3_tip_dynamic_read_leveling()
425 u32 bus_num, if_id, cl_val, bit_num; in ddr3_tip_dynamic_per_bit_read_leveling() local
519 cl_val = in ddr3_tip_dynamic_per_bit_read_leveling()
520 cas_latency_table[speed_bin_index].cl_val[freq]; in ddr3_tip_dynamic_per_bit_read_leveling()
521 data = (cl_val << 17) | (0x3 << 25); in ddr3_tip_dynamic_per_bit_read_leveling()
1702 int cl_val = tm->interface_params[0].cas_l; in mv_ddr_rl_dqs_burst() local
1766 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
[all …]
Dddr3_training_ip.h117 u8 cl_val[DDR_FREQ_LAST]; member
Dddr3_training.c1334 cas_latency_table[speed_bin_index].cl_val[frequency]; in ddr3_tip_freq_set()
1337 cl_val[frequency]; in ddr3_tip_freq_set()
1349 cl_val[cnt_id])); in ddr3_tip_freq_set()