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Searched refs:clb (Results 1 – 23 of 23) sorted by relevance

/external/wpa_supplicant_8/src/fst/
Dfst_internal.h40 #define foreach_fst_ctrl_call(clb, ...) \ argument
45 if (__fst_ctrl_h->ctrl.clb) \
46 __fst_ctrl_h->ctrl.clb(__VA_ARGS__);\
Dfst_session.h53 void fst_session_enum(struct fst_group *g, fst_session_enum_clb clb, void *ctx);
Dfst_session.c1183 void fst_session_enum(struct fst_group *g, fst_session_enum_clb clb, void *ctx) in fst_session_enum() argument
1189 clb(s->group, s, ctx); in fst_session_enum()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_bit.txt6 # CHECK: r17 = clb(r21:20)
14 # CHECK: r17 = add(clb(r21:20),#23)
16 # CHECK: r17 = add(clb(r21),#23)
18 # CHECK: r17 = clb(r21)
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_bit.txt6 # CHECK: r17 = clb(r21:20)
14 # CHECK: r17 = add(clb(r21:20), #23)
16 # CHECK: r17 = add(clb(r21), #23)
18 # CHECK: r17 = clb(r21)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Drdf-cover-use.ll8 declare i32 @llvm.hexagon.S2.clb(i32) #0
18 %v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a1) #0
Drdf-def-mask.ll18 %v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a0)
47 declare i32 @llvm.hexagon.S2.clb(i32) #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_bit.ll13 ; CHECK: = clb({{.*}})
41 ; CHECK: = add(clb({{.*}}),#0)
48 ; CHECK: = add(clb({{.*}}),#0)
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_bit.ll13 ; CHECK: = clb({{.*}})
41 ; CHECK: = add(clb({{.*}}), #0)
48 ; CHECK: = add(clb({{.*}}), #0)
/external/u-boot/drivers/ata/
Ddwc_ahsata.c25 u32 clb; member
484 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); in ahci_port_start()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td2334 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2349 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
DHexagonInstrInfo.td4145 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
4146 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
/external/honggfuzz/examples/apache-httpd/corpus_http1/
De9943ebcfb88d2c1cd8e1d66f72d93fb.0000fd65.honggfuzz.cov115 …/Quϕyn�lJ��K��Y5ʜ� ��w־:��<T��f�MR,ԭ���Ft��d=�#�#�����G�E�>(3clb;�V�(��R4ѭ�К t��6�…
D67154715f57204df236d04030732b84d.000eb1d3.honggfuzz.cov956 …�dlJh�˩���$H�� I�Z�f�zn��J�X�p�ӆXK!��)�|8T]�?[Og�Z�h�M� )����y:�;��dz2clb�~-�?�mg�ctf� )�|…
/external/honggfuzz/examples/apache-httpd/corpus_http2/
De9943ebcfb88d2c1cd8e1d66f72d93fb.0000fd65.honggfuzz.cov115 …/Quϕyn�lJ��K��Y5ʜ� ��w־:��<T��f�MR,ԭ���Ft��d=�#�#�����G�E�>(3clb;�V�(��R4ѭ�К t��6�…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td18582 "$Rd32 = clb($Rs32)",
18604 "$Rd32 = clb($Rss32)",
21996 "$Rd32 = add(clb($Rs32),#$Ii)",
22007 "$Rd32 = add(clb($Rss32),#$Ii)",
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1964 hexagon_S2_clb, // llvm.hexagon.S2.clb
DIntrinsicImpl.inc1990 "llvm.hexagon.S2.clb",
10868 1, // llvm.hexagon.S2.clb
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen1404 hexagon_S2_clb, // llvm.hexagon.S2.clb
7462 "llvm.hexagon.S2.clb",
15402 1, // llvm.hexagon.S2.clb
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen1404 hexagon_S2_clb, // llvm.hexagon.S2.clb
7462 "llvm.hexagon.S2.clb",
15402 1, // llvm.hexagon.S2.clb
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen1404 hexagon_S2_clb, // llvm.hexagon.S2.clb
7462 "llvm.hexagon.S2.clb",
15402 1, // llvm.hexagon.S2.clb
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen1398 hexagon_S2_clb, // llvm.hexagon.S2.clb
7422 "llvm.hexagon.S2.clb",
15307 1, // llvm.hexagon.S2.clb
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen1404 hexagon_S2_clb, // llvm.hexagon.S2.clb
7462 "llvm.hexagon.S2.clb",
15402 1, // llvm.hexagon.S2.clb