Searched refs:clk_base (Results 1 – 4 of 4) sorted by relevance
149 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_enable() argument153 data = readl(clk_base); in hi6220_clk_enable()156 writel(bitfield, clk_base); in hi6220_clk_enable()158 data = readl(clk_base + STAT_EN_OFF); in hi6220_clk_enable()165 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_disable() argument169 data = readl(clk_base); in hi6220_clk_disable()172 writel(data, clk_base); in hi6220_clk_disable()174 data = readl(clk_base + STAT_DIS_OFF); in hi6220_clk_disable()
379 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()417 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
577 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()614 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
80 u8 clk_base[2]; /* Clock Frequency Base Reg */ member