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Searched refs:clk_debug (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx7ulp/
Dpcc.c92 clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n", in pcc_clock_enable()
105 clk_debug("pcc_clock_enable: val 0x%x\n", val); in pcc_clock_enable()
141 clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n", in pcc_clock_sel()
155 clk_debug("pcc_clock_sel: val 0x%x\n", val); in pcc_clock_sel()
230 clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n", in pcc_clock_get_clksrc()
248 clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src); in pcc_clock_get_clksrc()
265 clk_debug("pcc_clock_get_rate: parent rate %u\n", rate); in pcc_clock_get_rate()
281 clk_debug("pcc_clock_get_rate: rate %u\n", rate); in pcc_clock_get_rate()
Dscg.c204 clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg); in scg_apll_pfd_get_rate()
211 clk_debug("scg_apll_pfd_get_rate rate %u\n", rate); in scg_apll_pfd_get_rate()
254 clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg); in scg_spll_pfd_get_rate()
261 clk_debug("scg_spll_pfd_get_rate rate %u\n", rate); in scg_spll_pfd_get_rate()
301 clk_debug("scg_spll_get_rate reg 0x%x\n", reg); in scg_spll_get_rate()
315 clk_debug("scg_spll_get_rate SPLL %u\n", rate); in scg_spll_get_rate()
323 clk_debug("scg_spll_get_rate PFD %u\n", rate); in scg_spll_get_rate()
361 clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg); in scg_nic_get_rate()
368 clk_debug("scg_nic_get_rate parent rate %u\n", rate); in scg_nic_get_rate()
374 clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); in scg_nic_get_rate()
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/external/u-boot/arch/arm/include/asm/arch-mx7ulp/
Dscg.h12 #define clk_debug(fmt, args...) printf(fmt, ##args) macro
14 #define clk_debug(fmt, args...) macro