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/external/u-boot/arch/arm/dts/
Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
31 clock-mult = <1>;
[all …]
Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
39 clock-mult = <1>;
[all …]
Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
[all …]
Ddra7xx-clocks.dtsi2 * Device Tree Source for DRA7xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
[all …]
Dkeystone-clocks.dtsi2 * Device Tree Source for Keystone 2 clock tree
17 #clock-cells = <0>;
18 compatible = "ti,keystone,pll-mux-clock";
23 clock-output-names = "mainmuxclk";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
30 clock-div = <1>;
31 clock-mult = <1>;
32 clock-output-names = "chipclk1";
36 #clock-cells = <0>;
[all …]
Dkeystone-k2hk-clocks.dtsi4 * Keystone 2 Kepler/Hawking SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
Ddm816x-clocks.dtsi9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
15 clock-output-names = "main_pll_clk1",
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP34xx/OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-no-wait-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,composite-divider-clock";
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
38 clock-mult = <1>;
[all …]
Dkeystone-k2l-clocks.dtsi4 * Keystone 2 lamarr SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <3>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <5>;
29 #clock-cells = <0>;
[all …]
Domap34xx-omap36xx-clocks.dtsi2 * Device Tree Source for OMAP34XX/OMAP36XX clock data
12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
36 #clock-cells = <0>;
[all …]
Dsama5d2.dtsi16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <0>;
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <0>;
38 clock-names = "ohci_clk", "hclk", "uhpck";
46 clock-names = "usb_clk", "ehci_clk";
54 clock-names = "hclock", "multclk", "baseclk";
62 clock-names = "hclock", "multclk", "baseclk";
[all …]
Dzynqmp-clk.dtsi12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <100000000>;
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <125000000>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <200000000>;
32 compatible = "fixed-clock";
[all …]
Dstih410-clock.dtsi8 #include <dt-bindings/clock/stih410-clks.h>
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
28 * ARM Peripheral clock for timers
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
34 clock-div = <2>;
35 clock-mult = <1>;
[all …]
Dstih407-clock.dtsi8 #include <dt-bindings/clock/stih407-clks.h>
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <30000000>;
25 * ARM Peripheral clock for timers
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
32 clock-div = <2>;
33 clock-mult = <1>;
44 #clock-cells = <1>;
[all …]
Dam35xx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "ti,am35xx-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,gate-clock";
28 #clock-cells = <0>;
29 compatible = "ti,am35xx-gate-clock";
36 #clock-cells = <0>;
37 compatible = "ti,gate-clock";
44 #clock-cells = <0>;
[all …]
Dimx7ulp.dtsi9 #include <dt-bindings/clock/imx7ulp-clock.h>
80 ckil: clock@0 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
87 osc: clock@1 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
[all …]
Dsun5i.dtsi47 #include <dt-bindings/clock/sun4i-a10-pll2.h>
72 * This is a dummy clock, to be used as placeholder on
73 * other mux clocks when a specific parent clock is not
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
84 #clock-cells = <0>;
87 clock-frequency = <24000000>;
88 clock-output-names = "osc24M";
92 compatible = "fixed-factor-clock";
[all …]
Dsun5i-gr8.dtsi45 #include <dt-bindings/clock/sun4i-a10-pll2.h>
72 * This is a dummy clock, to be used as placeholder on
73 * other mux clocks when a specific parent clock is not
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
84 #clock-cells = <0>;
87 clock-frequency = <24000000>;
88 clock-output-names = "osc24M";
92 compatible = "fixed-factor-clock";
[all …]
Dkeystone-k2e-clocks.dtsi13 #clock-cells = <0>;
14 compatible = "ti,keystone,main-pll-clock";
21 #clock-cells = <0>;
22 compatible = "ti,keystone,pll-clock";
24 clock-output-names = "papllclk";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";
39 #clock-cells = <0>;
40 compatible = "ti,keystone,psc-clock";
[all …]
Dsun4i-a10.dtsi48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
116 clock-latency = <244144>; /* 8 32k periods */
172 * This is a dummy clock, to be used as placeholder on
173 * other mux clocks when a specific parent clock is not
178 #clock-cells = <0>;
179 compatible = "fixed-clock";
180 clock-frequency = <0>;
184 #clock-cells = <0>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc24M";
[all …]
/external/webrtc/webrtc/modules/video_coding/
Dtiming_unittest.cc28 SimulatedClock clock(0); in TEST() local
29 VCMTiming timing(&clock); in TEST()
41 timing.IncomingTimestamp(timeStamp, clock.TimeInMilliseconds()); in TEST()
47 timing.RenderTimeMs(timeStamp, clock.TimeInMilliseconds()), in TEST()
48 clock.TimeInMilliseconds()); in TEST()
55 clock.AdvanceTimeMilliseconds(1000); in TEST()
59 timing.RenderTimeMs(timeStamp, clock.TimeInMilliseconds()), in TEST()
60 clock.TimeInMilliseconds()); in TEST()
65 clock.AdvanceTimeMilliseconds(1000); in TEST()
68 timing.RenderTimeMs(timeStamp, clock.TimeInMilliseconds()), in TEST()
[all …]
/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_gen5.c320 u32 reg, clock; in cm_get_main_vco_clk_hz() local
324 clock = cm_get_osc_clk_hz(1); in cm_get_main_vco_clk_hz()
325 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> in cm_get_main_vco_clk_hz()
327 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> in cm_get_main_vco_clk_hz()
330 return clock; in cm_get_main_vco_clk_hz()
335 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
342 clock = cm_get_osc_clk_hz(1); in cm_get_per_vco_clk_hz()
344 clock = cm_get_osc_clk_hz(2); in cm_get_per_vco_clk_hz()
346 clock = cm_get_f2s_per_ref_clk_hz(); in cm_get_per_vco_clk_hz()
350 clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> in cm_get_per_vco_clk_hz()
[all …]
Dclock_manager_s10.c237 unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz() local
239 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_mpu_clk_hz()
241 switch (clock) { in cm_get_mpu_clk_hz()
243 clock = cm_get_main_vco_clk_hz(); in cm_get_mpu_clk_hz()
244 clock /= (readl(&clock_manager_base->main_pll.pllc0) & in cm_get_mpu_clk_hz()
249 clock = cm_get_per_vco_clk_hz(); in cm_get_mpu_clk_hz()
250 clock /= (readl(&clock_manager_base->per_pll.pllc0) & in cm_get_mpu_clk_hz()
255 clock = cm_get_osc_clk_hz(); in cm_get_mpu_clk_hz()
259 clock = cm_get_intosc_clk_hz(); in cm_get_mpu_clk_hz()
263 clock = cm_get_fpga_clk_hz(); in cm_get_mpu_clk_hz()
[all …]
/external/u-boot/arch/nios2/dts/
D10m50_devboard.dts39 clock-frequency = <75000000>;
74 clock-frequency = <50000000>;
136 enet_pll: clock@0 {
138 #clock-cells = <1>;
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <125000000>;
144 clock-output-names = "enet_pll-c0";
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
[all …]

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