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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dclz.s10 clz z31.b, p7/m, z31.b label
16 clz z31.h, p7/m, z31.h label
22 clz z31.s, p7/m, z31.s label
28 clz z31.d, p7/m, z31.d label
44 clz z4.d, p7/m, z31.d label
56 clz z4.d, p7/m, z31.d label
/external/tensorflow/tensorflow/core/lib/strings/
Dscanner.h68 Scanner& One(CharClass clz) { in One() argument
69 if (cur_.empty() || !Matches(clz, cur_[0])) { in One()
95 Scanner& Any(CharClass clz) { in Any() argument
96 while (!cur_.empty() && Matches(clz, cur_[0])) { in Any()
103 Scanner& Many(CharClass clz) { return One(clz).Any(clz); } in Many() argument
186 static bool Matches(CharClass clz, char ch) { in Matches() argument
187 switch (clz) { in Matches()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dctlz.ll10 ; llvm.ctlz.i32(%a, false), as ptx's clz(0) is defined to return 0.
15 ; CHECK-NEXT: clz.b32
24 ; CHECK-NEXT: clz.b32
31 ; PTX's clz.b64 returns a 32-bit value, but LLVM's intrinsic returns a 64-bit
36 ; CHECK-NEXT: clz.b64
46 ; CHECK-NEXT: clz.b64
55 ; natural return width of ptx's clz.b64 instruction. No conversions should be
60 ; CHECK-NEXT: clz.b64
70 ; CHECK-NEXT: clz.b64
86 ; CHECK-NEXT: clz.b32
[all …]
/external/llvm/test/CodeGen/ARM/
Dcttz.ll17 ; CHECK: clz
26 ; CHECK: clz
34 ; CHECK: clz
44 ; CHECK: clz
57 ; CHECK: clz
66 ; CHECK: clz
75 ; CHECK: clz
85 ; CHECK: clz
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcttz.ll17 ; CHECK: clz
26 ; CHECK: clz
34 ; CHECK: clz
43 ; CHECK: clz
57 ; CHECK: clz
66 ; CHECK: clz
75 ; CHECK: clz
84 ; CHECK: clz
Dand-load-combine.ll14 ; ARM-NEXT: clz r0, r0
23 ; ARMEB-NEXT: clz r0, r0
42 ; THUMB2-NEXT: clz r0, r0
61 ; ARM-NEXT: clz r0, r0
70 ; ARMEB-NEXT: clz r0, r0
89 ; THUMB2-NEXT: clz r0, r0
109 ; ARM-NEXT: clz r0, r0
118 ; ARMEB-NEXT: clz r0, r0
137 ; THUMB2-NEXT: clz r0, r0
156 ; ARM-NEXT: clz r0, r0
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dctlz.ll10 ; CHECK: clz.b32
16 ; CHECK: clz.b32
22 ; CHECK: clz.b64
29 ; CHECK: clz.b32
35 ; CHECK: clz.b32
41 ; CHECK: clz.b64
/external/libhevc/decoder/
Dihevcd_parse_residual.c665 UWORD32 clz; in ihevcd_parse_residual_coding() local
666 clz = CLZ(u4_sig_coeff_map); in ihevcd_parse_residual_coding()
667 n = 31 - clz; in ihevcd_parse_residual_coding()
668 u4_sig_coeff_map_shift = u4_sig_coeff_map << clz; in ihevcd_parse_residual_coding()
722 clz = CLZ(u4_sig_coeff_map_shift); in ihevcd_parse_residual_coding()
723 u4_sig_coeff_map_shift <<= clz; in ihevcd_parse_residual_coding()
724 n -= (WORD32)clz; in ihevcd_parse_residual_coding()
771 UWORD32 clz; in ihevcd_parse_residual_coding() local
773 clz = CLZ(u4_sig_coeff_map); in ihevcd_parse_residual_coding()
774 n = 31 - clz; in ihevcd_parse_residual_coding()
[all …]
Dihevcd_cabac.c242 WORD32 clz; in ihevcd_cabac_decode_bin() local
251 clz = CLZ(u4_range); in ihevcd_cabac_decode_bin()
252 clz -= (32 - RANGE_NUMBITS); in ihevcd_cabac_decode_bin()
253 u4_qnt_range = u4_range << clz; in ihevcd_cabac_decode_bin()
261 u4_rlps = u4_rlps << (RANGE_SHIFT - clz); in ihevcd_cabac_decode_bin()
381 WORD32 clz; in ihevcd_cabac_decode_terminate() local
386 clz = CLZ(u4_range); in ihevcd_cabac_decode_terminate()
387 clz -= (32 - RANGE_NUMBITS); in ihevcd_cabac_decode_terminate()
388 u4_range -= 2 << (RANGE_SHIFT - clz); in ihevcd_cabac_decode_terminate()
400 WORD32 clz; in ihevcd_cabac_decode_terminate() local
[all …]
Dihevcd_cabac.h66 WORD32 clz; \
74 clz = CLZ(u4_range); \
75 clz -= (32 - RANGE_NUMBITS); \
76 u4_qnt_range = u4_range << clz; \
80 u4_rlps = u4_rlps << (RANGE_SHIFT - clz); \
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vclz.ll5 ; CHECK: clz.8b v0, v0
13 ; CHECK: clz.8b v0, v0
21 ; CHECK: clz.4h v0, v0
29 ; CHECK: clz.4h v0, v0
37 ; CHECK: clz.2s v0, v0
45 ; CHECK: clz.2s v0, v0
65 ; CHECK: clz.16b v0, v0
73 ; CHECK: clz.16b v0, v0
81 ; CHECK: clz.8h v0, v0
89 ; CHECK: clz.8h v0, v0
[all …]
Ddp1.ll53 ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
62 ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
71 ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
80 ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
90 ; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
100 ; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
110 ; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
120 ; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
/external/llvm/test/CodeGen/AArch64/
Darm64-vclz.ll5 ; CHECK: clz.8b v0, v0
13 ; CHECK: clz.8b v0, v0
21 ; CHECK: clz.4h v0, v0
29 ; CHECK: clz.4h v0, v0
37 ; CHECK: clz.2s v0, v0
45 ; CHECK: clz.2s v0, v0
65 ; CHECK: clz.16b v0, v0
73 ; CHECK: clz.16b v0, v0
81 ; CHECK: clz.8h v0, v0
89 ; CHECK: clz.8h v0, v0
[all …]
Ddp1.ll53 ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
62 ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
71 ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
80 ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
90 ; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
100 ; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
110 ; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
120 ; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
/external/aac/libSACdec/src/
Dsac_reshapeBBEnv.cpp245 INT qs, clz; in getMaxValDmx() local
256 clz = fixMax(0, CntLeadingZeros(maxVal) - 1); in getMaxValDmx()
258 return (clz); in getMaxValDmx()
268 INT qs, clz; in getMaxValDryWet() local
282 clz = fixMax(0, CntLeadingZeros(maxVal) - 1); in getMaxValDryWet()
284 return (clz); in getMaxValDryWet()
342 INT clz, scale, scale_min, envSF; in extractBBEnv() local
389 clz = getMaxValDryWet( in extractBBEnv()
397 clz = getMaxValDmx(pReal, pImag, cplxBands, hybBands); in extractBBEnv()
408 getSlotNrgHQ(&pReal[12], &pImag[12], slotNrg, clz, in extractBBEnv()
[all …]
/external/u-boot/arch/arm/lib/
Duldivmod.S57 @ D_0 = clz A
59 clz D_0, A_1
62 @ D_1 = clz B
64 clz D_1, B_1
67 @ if clz B - clz A > 0
70 @ B <<= (clz B - clz A)
79 @ C = 1 << (clz B - clz A)
176 clz D_0, B_0
180 clz D_0, B_1
/external/llvm/test/CodeGen/Mips/
Dctlz-v.ll8 ; MIPS32: clz $2, $4
9 ; MIPS32: clz $3, $5
12 ; MIPS64-DAG: clz $2, $[[A0]]
14 ; MIPS64-DAG: clz $3, $[[A1]]
Dcttz-v.ll11 ; MIPS32-DAG: clz $[[R3:[0-9]+]], $[[R2]]
17 ; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]]
25 ; MIPS64-DAG: clz $[[R3:[0-9]+]], $[[R2]]
32 ; MIPS64-DAG: clz $[[R8:[0-9]+]], $[[R7]]
Dcountleading.ll19 ; MIPS4-NOT: clz
21 ; MIPS32-GT-R1: clz $2, $4
23 ; MIPS64-GT-R1: clz $2, $4
25 ; MICROMIPS64: clz $2, $4
56 ; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
57 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dctlz-v.ll8 ; MIPS32: clz $2, $4
9 ; MIPS32: clz $3, $5
13 ; MIPS64-DAG: clz $[[R0:[0-9]+]], $[[A1]]
16 ; MIPS64-DAG: clz $[[R2:[0-9]+]], $[[A2]]
Dcttz-v.ll11 ; MIPS32-DAG: clz $[[R3:[0-9]+]], $[[R2]]
17 ; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]]
25 ; MIPS64-DAG: clz $[[R3:[0-9]+]], $[[R2]]
34 ; MIPS64-DAG: clz $[[R12:[0-9]+]], $[[R11]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-objdump/ARM/
Dv5t-subarch.s5 clz: label
6 clz r0, r1 label
8 @ CHECK-LABEL: clz
/external/compiler-rt/lib/builtins/
Dfloatundixf.c34 int clz = __builtin_clzll(a); in __floatundixf() local
35 int e = (N - 1) - clz ; /* exponent */ in __floatundixf()
38 fb.u.low.all = a << clz; /* mantissa */ in __floatundixf()
Dfloatdixf.c37 int clz = __builtin_clzll(a); in __floatdixf() local
38 int e = (N - 1) - clz ; /* exponent */ in __floatdixf()
42 fb.u.low.all = a << clz; /* mantissa */ in __floatdixf()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dthumb2-tst.ll64 ; CHECK-NEXT: clz r0, r0
75 ; CHECK-NEXT: clz r0, r0
86 ; CHECK-NEXT: clz r0, r0
97 ; CHECK-NEXT: clz r0, r0
108 ; CHECK-NEXT: clz r0, r0

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