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Searched refs:cmask (Results 1 – 24 of 24) sorted by relevance

/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnv30_state.c44 uint32_t blend[2], cmask[2]; in nv30_blend_state_create() local
65 cmask[0] = !!(cso->rt[0].colormask & PIPE_MASK_A) << 24 | in nv30_blend_state_create()
71 cmask[1] = 0; in nv30_blend_state_create()
74 cmask[1] |= !!(cso->rt[i].colormask & PIPE_MASK_A) << (0 + (i * 4)) | in nv30_blend_state_create()
81 cmask[1] = 0x00001110 * !!(cmask[0] & 0x01000000); in nv30_blend_state_create()
82 cmask[1] |= 0x00002220 * !!(cmask[0] & 0x00010000); in nv30_blend_state_create()
83 cmask[1] |= 0x00004440 * !!(cmask[0] & 0x00000100); in nv30_blend_state_create()
84 cmask[1] |= 0x00008880 * !!(cmask[0] & 0x00000001); in nv30_blend_state_create()
90 SB_DATA (so, cmask[1]); in nv30_blend_state_create()
114 SB_DATA (so, cmask[0]); in nv30_blend_state_create()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c42 assert(rtex->cmask.size == 0); in si_alloc_separate_cmask()
44 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask); in si_alloc_separate_cmask()
45 if (!rtex->cmask.size) in si_alloc_separate_cmask()
52 rtex->cmask.size, in si_alloc_separate_cmask()
53 rtex->cmask.alignment); in si_alloc_separate_cmask()
55 rtex->cmask.size = 0; in si_alloc_separate_cmask()
60 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; in si_alloc_separate_cmask()
456 if (tex->resource.b.b.nr_samples >= 2 && tex->cmask.size) { in si_do_fast_color_clear()
462 tex->cmask.offset, tex->cmask.size, in si_do_fast_color_clear()
488 if (tex->cmask.size == 0) { in si_do_fast_color_clear()
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Dsi_blit.c534 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) in si_decompress_color_texture()
842 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) { in si_decompress_subresource()
1122 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */ in do_hardware_msaa_resolve()
1302 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) { in si_flush_resource()
Dsi_state.c3034 meta = tex->surface.u.gfx9.cmask; in si_emit_framebuffer_state()
3054 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */ in si_emit_framebuffer_state()
3055 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */ in si_emit_framebuffer_state()
3113 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */ in si_emit_framebuffer_state()
3114 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */ in si_emit_framebuffer_state()
3804 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) | in si_make_texture_descriptor()
3805 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned); in si_make_texture_descriptor()
Dsi_descriptors.c479 (rtex->cmask.size || rtex->dcc_offset)); in color_needs_decompression()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) { in r600_prepare_for_dma_blit()
89 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level)) in r600_prepare_for_dma_blit()
336 if (!rtex->cmask.size) in r600_texture_discard_cmask()
342 memset(&rtex->cmask, 0, sizeof(rtex->cmask)); in r600_texture_discard_cmask()
343 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
424 rtex->cmask = new_tex->cmask; in r600_reallocate_texture_inplace()
435 assert(!rtex->cmask.size); in r600_reallocate_texture_inplace()
482 rtex->cmask.size) { in r600_texture_get_handle()
489 if (rtex->cmask.size) in r600_texture_get_handle()
686 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask); in r600_texture_allocate_cmask()
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Dr600_blit.c394 assert(tex->cmask.size); in r600_decompress_color_textures()
418 assert(tex->cmask.size); in r600_decompress_color_images()
458 } else if (rtex->cmask.size) { in r600_decompress_subresource()
862 (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) { in do_hardware_msaa_resolve()
970 if (!rtex->is_depth && rtex->cmask.size) { in r600_flush_resource()
Dr600_state.c959 if (rtex->cmask.size) { in r600_init_color_surface()
960 surf->cb_color_cmask = rtex->cmask.offset >> 8; in r600_init_color_surface()
961 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max); in r600_init_color_surface()
977 struct r600_cmask_info cmask; in r600_init_color_surface() local
980 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask); in r600_init_color_surface()
985 rctx->dummy_cmask->b.b.width0 < cmask.size || in r600_init_color_surface()
986 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) { in r600_init_color_surface()
994 cmask.size, cmask.alignment); in r600_init_color_surface()
1003 memset(ptr, 0xCC, cmask.size); in r600_init_color_surface()
1029 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) | in r600_init_color_surface()
Dr600_pipe_common.h224 struct r600_cmask_info cmask; member
Dr600_state_common.c665 if (!is_buffer && rtex->cmask.size) { in r600_set_sampler_views()
715 if (rtex->cmask.size) { in r600_update_compressed_colortex_mask()
767 if (rtex->cmask.size) { in r600_update_compressed_colortex_mask_images()
Devergreen_state.c1739 …radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0… in evergreen_emit_image_state()
1740 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */ in evergreen_emit_image_state()
1869 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ in evergreen_emit_framebuffer_state()
1870 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ in evergreen_emit_framebuffer_state()
4125 if (!is_buffer && rtex->cmask.size) in evergreen_set_shader_images()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_texture.c85 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) { in si_prepare_for_dma_blit()
97 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level)) in si_prepare_for_dma_blit()
404 if (!rtex->cmask.size) in r600_texture_discard_cmask()
410 memset(&rtex->cmask, 0, sizeof(rtex->cmask)); in r600_texture_discard_cmask()
411 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
555 rtex->cmask = new_tex->cmask; in r600_reallocate_texture_inplace()
567 assert(!rtex->cmask.size); in r600_reallocate_texture_inplace()
726 (rtex->cmask.size || rtex->dcc_offset)) { in r600_texture_get_handle()
735 if (rtex->cmask.size) in r600_texture_get_handle()
955 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask); in r600_texture_allocate_cmask()
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Dr600_pipe_common.h218 struct r600_cmask_info cmask; member
/external/mesa3d/src/amd/vulkan/
Dradv_image.c560 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) | in si_make_texture_descriptor()
561 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned); in si_make_texture_descriptor()
782 radv_image_get_cmask_info(device, image, &image->cmask); in radv_image_alloc_cmask()
784 image->cmask.offset = align64(image->size, image->cmask.alignment); in radv_image_alloc_cmask()
787 image->clear_value_offset = image->cmask.offset + image->cmask.size; in radv_image_alloc_cmask()
790 image->size = image->cmask.offset + image->cmask.size + clear_value_size; in radv_image_alloc_cmask()
791 image->alignment = MAX2(image->alignment, image->cmask.alignment); in radv_image_alloc_cmask()
Dradv_meta_clear.c957 if (!iview->image->cmask.size && !iview->image->surface.dcc_size) in emit_fast_color_clear()
1030 iview->image->offset + iview->image->cmask.offset, in emit_fast_color_clear()
1031 iview->image->cmask.size, 0); in emit_fast_color_clear()
Dradv_cmd_buffer.c1457 assert(image->cmask.size || image->surface.dcc_size); in radv_set_color_clear_regs()
1481 if (!image->cmask.size && !image->surface.dcc_size) in radv_load_color_clear_regs()
3965 image->offset + image->cmask.offset, in radv_initialise_cmask()
3966 image->cmask.size, value); in radv_initialise_cmask()
4064 if (image->cmask.size || image->fmask.size) in radv_handle_image_transition()
Dradv_device.c3111 meta = iview->image->surface.u.gfx9.cmask; in radv_initialise_color_surface()
3134 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max; in radv_initialise_color_surface()
3154 va += iview->image->cmask.offset; in radv_initialise_color_surface()
3231 if (iview->image->cmask.size && in radv_initialise_color_surface()
Dradv_private.h1385 struct radv_cmask_info cmask; member
/external/mesa3d/src/amd/common/
Dac_surface.h130 struct gfx9_surf_meta_flags cmask; /* metadata of fmask */ member
Dac_surface.c1048 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned; in gfx9_compute_miptree()
1049 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned; in gfx9_compute_miptree()
/external/kernel-headers/original/uapi/sound/
Dasound.h404 unsigned int cmask; /* R: changed masks */ member
/external/tinyalsa/
Dpcm.c237 p->cmask = 0; in param_init()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_vgpu10.c3254 unsigned cmask = plane_mask & VGPU10_OPERAND_4_COMPONENT_MASK_ALL; in emit_clip_distance_declarations() local
3256 VGPU10_NAME_CLIP_DISTANCE, cmask); in emit_clip_distance_declarations()
3260 unsigned cmask = (plane_mask >> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL; in emit_clip_distance_declarations() local
3262 VGPU10_NAME_CLIP_DISTANCE, cmask); in emit_clip_distance_declarations()
/external/neon_2_sse/
DNEON_2_SSE.h4239 …_NEON2SSE_ALIGN_16 static const uint16_t cmask[] = {0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000… in vqdmulhq_s16() local
4245 mask = _mm_cmpeq_epi16 (res, *(__m128i*)cmask); in vqdmulhq_s16()
4304 …_NEON2SSE_ALIGN_16 static const uint16_t cmask[] = {0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000… in vqrdmulhq_s16() local
4306 mask = _mm_cmpeq_epi16 (res, *(__m128i*)cmask); in vqrdmulhq_s16()
4995 …_NEON2SSE_ALIGN_16 static const uint32_t cmask[] = {0x80000000, 0x80000000, 0x80000000, 0x80000000… in vqdmlsl_s16() local
4998 mask = _mm_cmpeq_epi32 (res32, *(__m128i*)cmask); in vqdmlsl_s16()
5008 _NEON2SSE_ALIGN_16 static const uint64_t cmask[] = {0x8000000000000000, 0x8000000000000000}; in _NEON2SSE_PERFORMANCE_WARNING() local
5011 mask = _MM_CMPEQ_EPI64 (res64, *(__m128i*)cmask); in _NEON2SSE_PERFORMANCE_WARNING()
12766 …_NEON2SSE_ALIGN_16 static const uint32_t cmask[] = {0x80000000, 0x80000000, 0x80000000, 0x80000000… variable
12772 mask = _mm_cmpeq_epi32 (res, *(__m128i*)cmask);