Searched refs:cmp_instr (Results 1 – 3 of 3) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_nir.cpp | 1012 nir_alu_instr *cmp_instr = in optimize_predicate() local
1015 switch (cmp_instr->op) { in optimize_predicate()
1037 brw_swizzle_for_size(nir_op_infos[cmp_instr->op].input_sizes[0]); in optimize_predicate()
1040 assert(nir_op_infos[cmp_instr->op].num_inputs == 2); in optimize_predicate()
1042 nir_alu_type type = nir_op_infos[cmp_instr->op].input_types[i]; in optimize_predicate()
1043 unsigned bit_size = nir_src_bit_size(cmp_instr->src[i].src); in optimize_predicate()
1045 op[i] = get_nir_src(cmp_instr->src[i].src, type, 4); in optimize_predicate()
1047 brw_swizzle_for_nir_swizzle(cmp_instr->src[i].swizzle); in optimize_predicate()
1049 op[i].abs = cmp_instr->src[i].abs; in optimize_predicate()
1050 op[i].negate = cmp_instr->src[i].negate; in optimize_predicate()
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| /external/v8/src/compiler/s390/ |
| D | code-generator-s390.cc | 509 #define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr) \ argument
518 __ cmp_instr(i.InputRegister(0), operand); \
524 __ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
530 __ cmp_instr(i.InputRegister(0), i.InputImmediate(1)); \
537 __ cmp_instr(i.InputRegister(0), i.InputStackSlot(1)); \
542 #define ASSEMBLE_COMPARE32(cmp_instr, cmpl_instr) \ argument
551 __ cmp_instr(i.InputRegister(0), operand); \
557 __ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
563 __ cmp_instr(i.InputRegister(0), i.InputImmediate(1)); \
570 __ cmp_instr(i.InputRegister(0), i.InputStackSlot32(1)); \
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| /external/v8/src/compiler/ppc/ |
| D | code-generator-ppc.cc | 384 #define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr) \ argument
391 __ cmp_instr(i.InputRegister(0), i.InputRegister(1), cr); \
397 __ cmp_instr##i(i.InputRegister(0), i.InputImmediate(1), cr); \
404 #define ASSEMBLE_FLOAT_COMPARE(cmp_instr) \ argument
407 __ cmp_instr(i.InputDoubleRegister(0), i.InputDoubleRegister(1), cr); \
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