| /external/kernel-headers/original/uapi/rdma/ |
| D | mlx5-abi.h | 90 __u32 comp_mask; member
139 __u32 comp_mask; member
252 __u32 comp_mask; member
353 __u32 comp_mask; member
367 __u32 comp_mask; member
376 __u32 comp_mask; member
393 __u32 comp_mask; member
412 __u32 comp_mask; member
433 __u32 comp_mask; member
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| D | ib_user_verbs.h | 220 __u32 comp_mask; member
261 __u32 comp_mask; member
422 __u32 comp_mask; member
435 __u32 comp_mask; member
615 __u32 comp_mask; member
646 __u32 comp_mask; member
747 __u32 comp_mask; member
1143 __u32 comp_mask; member
1149 __u32 comp_mask; member
1154 __u32 comp_mask; member
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| D | mlx4-abi.h | 108 __u32 comp_mask; member
127 __u32 comp_mask; member
131 __u32 comp_mask; member
182 __u32 comp_mask; member
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_shader.cpp | 62 void shader::add_pinned_gpr_values(vvec& vec, unsigned gpr, unsigned comp_mask, in add_pinned_gpr_values() argument
65 while (comp_mask) { in add_pinned_gpr_values()
66 if (comp_mask & 1) { in add_pinned_gpr_values()
80 comp_mask >>= 1; in add_pinned_gpr_values()
197 void shader::add_input(unsigned gpr, bool preloaded, unsigned comp_mask) { in add_input() argument
203 i.comp_mask = comp_mask; in add_input()
206 add_pinned_gpr_values(root->dst, gpr, comp_mask, true); in add_input()
224 add_pinned_gpr_values(cf->dst, gpr, I->comp_mask, false); in init_call_fs()
226 add_pinned_gpr_values(cf->src, gpr, I->comp_mask, true); in init_call_fs()
392 unsigned comp_mask) { in add_gpr_array() argument
[all …]
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| D | sb_shader.h | 40 unsigned comp_mask; member
331 void add_pinned_gpr_values(vvec& vec, unsigned gpr, unsigned comp_mask, bool src);
336 unsigned comp_mask);
344 unsigned comp_mask = 0xF);
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| D | sb_bc_builder.cpp | 343 .COMP_MASK(bc.comp_mask) in build_cf_mem()
354 .COMP_MASK(bc.comp_mask) in build_cf_mem()
365 .COMP_MASK(bc.comp_mask) in build_cf_mem()
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| D | sb_bc_decoder.cpp | 264 bc.comp_mask = w1.get_COMP_MASK(); in decode_cf_mem()
273 bc.comp_mask = w1.get_COMP_MASK(); in decode_cf_mem()
283 bc.comp_mask = w1.get_COMP_MASK(); in decode_cf_mem()
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| D | sb_bc_parser.cpp | 135 sh->add_gpr_array(a.gpr_start, a.gpr_count, a.comp_mask); in parse_decls()
147 sh->add_gpr_array(a.gpr_start, a.gpr_count, a.comp_mask); in parse_decls()
833 if (c->bc.comp_mask & (1 << s)) in prepare_ir()
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| D | sb_bc_dump.cpp | 149 s << ((n.bc.comp_mask & (1 << k)) ? chans[k] : '_'); in dump()
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| D | sb_bc.h | 474 unsigned comp_mask:4; member
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| D | sb_bc_finalize.cpp | 809 c->bc.comp_mask = mask; in finalize_cf()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | eg_asm.c | 114 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) | in eg_bytecode_cf_build()
131 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) | in eg_bytecode_cf_build()
171 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
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| D | r600_shader.h | 159 unsigned comp_mask; member
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| D | r600_asm.h | 145 unsigned comp_mask; member
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| D | r600_asm.c | 204 output->comp_mask == bc->cf_last->output.comp_mask && in r600_bytecode_add_output()
1688 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask); in r600_bytecode_cf_build()
2169 if (cf->output.comp_mask & (1 << i)) in r600_bytecode_disasm()
2777 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
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| D | r600_shader.c | 91 int size, unsigned comp_mask) { in r600_add_gpr_array() argument
105 ps->arrays[n].comp_mask = comp_mask; in r600_add_gpr_array()
2162 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i]; in emit_streamout()
2607 output.comp_mask = 0xF; in emit_gs_ring_writes()
8179 cf->output.comp_mask = 0xf; in tgsi_load_rat()
8323 cf->output.comp_mask = 1; in tgsi_store_buffer_rat()
8381 cf->output.comp_mask = 0xf; in tgsi_store_rat()
8556 cf->output.comp_mask = 0xf; in tgsi_atomic_op_rat()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 479 bits<4> comp_mask;
488 let Word1{15-12} = comp_mask;
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| D | R600Instructions.td | 273 let comp_mask = mask;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 489 bits<4> comp_mask;
498 let Word1{15-12} = comp_mask;
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| D | R600Instructions.td | 242 let comp_mask = mask;
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