| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 257 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
266 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
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| D | RegisterCoalescer.cpp | 288 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in isMoveInstr()
443 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
444 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
935 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), in reMaterializeTrivialDef()
1914 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
2306 TRI->composeSubRegIndices(SubIdx, MO.getSubReg()))) in usesLanes()
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| D | DetectDeadLanes.cpp | 181 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
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| D | TailDuplicator.cpp | 386 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(), in duplicateInstruction()
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| D | MachineInstr.cpp | 81 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 318 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
327 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
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| D | RegisterCoalescer.cpp | 322 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in INITIALIZE_PASS_DEPENDENCY()
477 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
478 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1151 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), in reMaterializeTrivialDef()
2255 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
2667 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
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| D | DetectDeadLanes.cpp | 179 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
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| D | TailDuplicator.cpp | 428 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(), in duplicateInstruction()
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| D | MachineOperand.cpp | 77 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 437 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 65 unsigned S = DFG.getTRI().composeSubRegIndices(DefR.Sub, I.SubIdx); in interpretAsCopy()
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| D | RDFGraph.cpp | 582 return TRI.composeSubRegIndices(RA.Sub, RB.Sub) == RA.Sub; in covers()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 554 unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 588 unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 1377 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || in CoalesceExtSubRegs()
1379 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { in CoalesceExtSubRegs()
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| D | MachineInstr.cpp | 121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
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| D | RegisterCoalescer.cpp | 220 return tri.composeSubRegIndices(a, b); in compose()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 93 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx); in getSubOperand64()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 2431 unsigned composeSubRegIndices(unsigned, unsigned) const;
4645 unsigned X86GenRegisterInfo::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {
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