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Searched refs:composeSubRegIndicesImpl (Results 1 – 6 of 6) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h557 return composeSubRegIndicesImpl(a, b); in composeSubRegIndices()
590 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { in composeSubRegIndicesImpl() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h591 return composeSubRegIndicesImpl(a, b); in composeSubRegIndices()
624 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { in composeSubRegIndicesImpl() function
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc3729 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
6054 unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc3876 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
6546 unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc3299 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
7319 unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc4980 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
8674 unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {