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Searched refs:control_core_control_spare_rw (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-omap2/omap5/
Dprcm-regs.c340 .control_core_control_spare_rw = 0x4A002E68,
432 .control_core_control_spare_rw = 0x4A002E68,
/external/u-boot/arch/arm/include/asm/
Domap_common.h438 u32 control_core_control_spare_rw; member
/external/u-boot/board/ti/dra7xx/
Devm.c835 clrsetbits_le32((*ctrl)->control_core_control_spare_rw, in recalibrate_iodelay()