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Searched refs:control_ddr3ch1_0 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-omap2/omap5/
Dprcm-regs.c326 .control_ddr3ch1_0 = 0x4A002E30,
418 .control_ddr3ch1_0 = 0x4A002E30,
Dhwinit.c77 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); in io_settings_ddr3()
/external/u-boot/arch/arm/include/asm/
Domap_common.h415 u32 control_ddr3ch1_0; member