• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * MPC8xx Internal Memory Map
3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4  *
5  * The I/O on the MPC860 is comprised of blocks of special registers
6  * and the dual port ram for the Communication Processor Module.
7  * Within this space are functional units such as the SIU, memory
8  * controller, system timers, and other control functions.  It is
9  * a combination that I found difficult to separate into logical
10  * functional files.....but anyone else is welcome to try.  -- Dan
11  */
12 #ifndef __IMMAP_8XX__
13 #define __IMMAP_8XX__
14 
15 /* System configuration registers.
16 */
17 typedef	struct sys_conf {
18 	uint	sc_siumcr;
19 	uint	sc_sypcr;
20 	uint	sc_swt;
21 	char	res1[2];
22 	ushort	sc_swsr;
23 	uint	sc_sipend;
24 	uint	sc_simask;
25 	uint	sc_siel;
26 	uint	sc_sivec;
27 	uint	sc_tesr;
28 	char	res2[0xc];
29 	uint	sc_sdcr;
30 	char	res3[0x4c];
31 } sysconf8xx_t;
32 
33 /* PCMCIA configuration registers.
34 */
35 typedef struct pcmcia_conf {
36 	uint	pcmc_pbr0;
37 	uint	pcmc_por0;
38 	uint	pcmc_pbr1;
39 	uint	pcmc_por1;
40 	uint	pcmc_pbr2;
41 	uint	pcmc_por2;
42 	uint	pcmc_pbr3;
43 	uint	pcmc_por3;
44 	uint	pcmc_pbr4;
45 	uint	pcmc_por4;
46 	uint	pcmc_pbr5;
47 	uint	pcmc_por5;
48 	uint	pcmc_pbr6;
49 	uint	pcmc_por6;
50 	uint	pcmc_pbr7;
51 	uint	pcmc_por7;
52 	char	res1[0x20];
53 	uint	pcmc_pgcra;
54 	uint	pcmc_pgcrb;
55 	uint	pcmc_pscr;
56 	char	res2[4];
57 	uint	pcmc_pipr;
58 	char	res3[4];
59 	uint	pcmc_per;
60 	char	res4[4];
61 } pcmconf8xx_t;
62 
63 /* Memory controller registers.
64 */
65 typedef struct	mem_ctlr {
66 	uint	memc_br0;
67 	uint	memc_or0;
68 	uint	memc_br1;
69 	uint	memc_or1;
70 	uint	memc_br2;
71 	uint	memc_or2;
72 	uint	memc_br3;
73 	uint	memc_or3;
74 	uint	memc_br4;
75 	uint	memc_or4;
76 	uint	memc_br5;
77 	uint	memc_or5;
78 	uint	memc_br6;
79 	uint	memc_or6;
80 	uint	memc_br7;
81 	uint	memc_or7;
82 	char	res1[0x24];
83 	uint	memc_mar;
84 	uint	memc_mcr;
85 	char	res2[4];
86 	uint	memc_mamr;
87 	uint	memc_mbmr;
88 	ushort	memc_mstat;
89 	ushort	memc_mptpr;
90 	uint	memc_mdr;
91 	char	res3[0x80];
92 } memctl8xx_t;
93 
94 /* System Integration Timers.
95 */
96 typedef struct	sys_int_timers {
97 	ushort	sit_tbscr;
98 	char	res0[0x02];
99 	uint	sit_tbreff0;
100 	uint	sit_tbreff1;
101 	char	res1[0x14];
102 	ushort	sit_rtcsc;
103 	char	res2[0x02];
104 	uint	sit_rtc;
105 	uint	sit_rtsec;
106 	uint	sit_rtcal;
107 	char	res3[0x10];
108 	ushort	sit_piscr;
109 	char	res4[2];
110 	uint	sit_pitc;
111 	uint	sit_pitr;
112 	char	res5[0x34];
113 } sit8xx_t;
114 
115 #define TBSCR_TBIRQ_MASK	((ushort)0xff00)
116 #define TBSCR_REFA		((ushort)0x0080)
117 #define TBSCR_REFB		((ushort)0x0040)
118 #define TBSCR_REFAE		((ushort)0x0008)
119 #define TBSCR_REFBE		((ushort)0x0004)
120 #define TBSCR_TBF		((ushort)0x0002)
121 #define TBSCR_TBE		((ushort)0x0001)
122 
123 #define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
124 #define RTCSC_SEC		((ushort)0x0080)
125 #define RTCSC_ALR		((ushort)0x0040)
126 #define RTCSC_38K		((ushort)0x0010)
127 #define RTCSC_SIE		((ushort)0x0008)
128 #define RTCSC_ALE		((ushort)0x0004)
129 #define RTCSC_RTF		((ushort)0x0002)
130 #define RTCSC_RTE		((ushort)0x0001)
131 
132 #define PISCR_PIRQ_MASK		((ushort)0xff00)
133 #define PISCR_PS		((ushort)0x0080)
134 #define PISCR_PIE		((ushort)0x0004)
135 #define PISCR_PTF		((ushort)0x0002)
136 #define PISCR_PTE		((ushort)0x0001)
137 
138 /* Clocks and Reset.
139 */
140 typedef struct clk_and_reset {
141 	uint	car_sccr;
142 	uint	car_plprcr;
143 	uint	car_rsr;
144 	char	res[0x74];        /* Reserved area                  */
145 } car8xx_t;
146 
147 /* System Integration Timers keys.
148 */
149 typedef struct sitk {
150 	uint	sitk_tbscrk;
151 	uint	sitk_tbreff0k;
152 	uint	sitk_tbreff1k;
153 	uint	sitk_tbk;
154 	char	res1[0x10];
155 	uint	sitk_rtcsck;
156 	uint	sitk_rtck;
157 	uint	sitk_rtseck;
158 	uint	sitk_rtcalk;
159 	char	res2[0x10];
160 	uint	sitk_piscrk;
161 	uint	sitk_pitck;
162 	char	res3[0x38];
163 } sitk8xx_t;
164 
165 /* Clocks and reset keys.
166 */
167 typedef struct cark {
168 	uint	cark_sccrk;
169 	uint	cark_plprcrk;
170 	uint	cark_rsrk;
171 	char	res[0x474];
172 } cark8xx_t;
173 
174 /* The key to unlock registers maintained by keep-alive power.
175 */
176 #define KAPWR_KEY	((unsigned int)0x55ccaa33)
177 
178 /* I2C
179 */
180 typedef struct i2c {
181 	u_char	i2c_i2mod;
182 	char	res1[3];
183 	u_char	i2c_i2add;
184 	char	res2[3];
185 	u_char	i2c_i2brg;
186 	char	res3[3];
187 	u_char	i2c_i2com;
188 	char	res4[3];
189 	u_char	i2c_i2cer;
190 	char	res5[3];
191 	u_char	i2c_i2cmr;
192 	char	res6[0x8b];
193 } i2c8xx_t;
194 
195 /* DMA control/status registers.
196 */
197 typedef struct sdma_csr {
198 	char	res1[4];
199 	uint	sdma_sdar;
200 	u_char	sdma_sdsr;
201 	char	res3[3];
202 	u_char	sdma_sdmr;
203 	char	res4[3];
204 	u_char	sdma_idsr1;
205 	char	res5[3];
206 	u_char	sdma_idmr1;
207 	char	res6[3];
208 	u_char	sdma_idsr2;
209 	char	res7[3];
210 	u_char	sdma_idmr2;
211 	char	res8[0x13];
212 } sdma8xx_t;
213 
214 /* Communication Processor Module Interrupt Controller.
215 */
216 typedef struct cpm_ic {
217 	ushort	cpic_civr;
218 	char	res[0xe];
219 	uint	cpic_cicr;
220 	uint	cpic_cipr;
221 	uint	cpic_cimr;
222 	uint	cpic_cisr;
223 } cpic8xx_t;
224 
225 /* Input/Output Port control/status registers.
226 */
227 typedef struct io_port {
228 	ushort	iop_padir;
229 	ushort	iop_papar;
230 	ushort	iop_paodr;
231 	ushort	iop_padat;
232 	char	res1[8];
233 	ushort	iop_pcdir;
234 	ushort	iop_pcpar;
235 	ushort	iop_pcso;
236 	ushort	iop_pcdat;
237 	ushort	iop_pcint;
238 	char	res2[6];
239 	ushort	iop_pddir;
240 	ushort	iop_pdpar;
241 	char	res3[2];
242 	ushort	iop_pddat;
243 	uint	utmode;
244 	char	res4[4];
245 } iop8xx_t;
246 
247 /* Communication Processor Module Timers
248 */
249 typedef struct cpm_timers {
250 	ushort	cpmt_tgcr;
251 	char	res1[0xe];
252 	ushort	cpmt_tmr1;
253 	ushort	cpmt_tmr2;
254 	ushort	cpmt_trr1;
255 	ushort	cpmt_trr2;
256 	ushort	cpmt_tcr1;
257 	ushort	cpmt_tcr2;
258 	ushort	cpmt_tcn1;
259 	ushort	cpmt_tcn2;
260 	ushort	cpmt_tmr3;
261 	ushort	cpmt_tmr4;
262 	ushort	cpmt_trr3;
263 	ushort	cpmt_trr4;
264 	ushort	cpmt_tcr3;
265 	ushort	cpmt_tcr4;
266 	ushort	cpmt_tcn3;
267 	ushort	cpmt_tcn4;
268 	ushort	cpmt_ter1;
269 	ushort	cpmt_ter2;
270 	ushort	cpmt_ter3;
271 	ushort	cpmt_ter4;
272 	char	res2[8];
273 } cpmtimer8xx_t;
274 
275 /* Finally, the Communication Processor stuff.....
276 */
277 typedef struct scc {		/* Serial communication channels */
278 	uint	scc_gsmrl;
279 	uint	scc_gsmrh;
280 	ushort	scc_psmr;
281 	char	res1[2];
282 	ushort	scc_todr;
283 	ushort	scc_dsr;
284 	ushort	scc_scce;
285 	char	res2[2];
286 	ushort	scc_sccm;
287 	char	res3;
288 	u_char	scc_sccs;
289 	char	res4[8];
290 } scc_t;
291 
292 typedef struct smc {		/* Serial management channels */
293 	char	res1[2];
294 	ushort	smc_smcmr;
295 	char	res2[2];
296 	u_char	smc_smce;
297 	char	res3[3];
298 	u_char	smc_smcm;
299 	char	res4[5];
300 } smc_t;
301 
302 /* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
303  * it fits within the address space.
304  */
305 
306 typedef struct fec {
307 	uint	fec_addr_low;		/* lower 32 bits of station address	*/
308 	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
309 	ushort	res1;			/* reserved				*/
310 	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
311 	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
312 	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
313 	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
314 	uint	fec_r_buff_size;	/* Rx buffer size			*/
315 	uint	res2[9];		/* reserved				*/
316 	uint	fec_ecntrl;		/* ethernet control register		*/
317 	uint	fec_ievent;		/* interrupt event register		*/
318 	uint	fec_imask;		/* interrupt mask register		*/
319 	uint	fec_ivec;		/* interrupt level and vector status	*/
320 	uint	fec_r_des_active;	/* Rx ring updated flag			*/
321 	uint	fec_x_des_active;	/* Tx ring updated flag			*/
322 	uint	res3[10];		/* reserved				*/
323 	uint	fec_mii_data;		/* MII data register			*/
324 	uint	fec_mii_speed;		/* MII speed control register		*/
325 	uint	res4[17];		/* reserved				*/
326 	uint	fec_r_bound;		/* end of RAM (read-only)		*/
327 	uint	fec_r_fstart;		/* Rx FIFO start address		*/
328 	uint	res5[6];		/* reserved				*/
329 	uint	fec_x_fstart;		/* Tx FIFO start address		*/
330 	uint	res6[17];		/* reserved				*/
331 	uint	fec_fun_code;		/* fec SDMA function code		*/
332 	uint	res7[3];		/* reserved				*/
333 	uint	fec_r_cntrl;		/* Rx control register			*/
334 	uint	fec_r_hash;		/* Rx hash register			*/
335 	uint	res8[14];		/* reserved				*/
336 	uint	fec_x_cntrl;		/* Tx control register			*/
337 	uint	res9[0x1e];		/* reserved				*/
338 } fec_t;
339 
340 typedef struct comm_proc {
341 	/* General control and status registers.
342 	*/
343 	ushort	cp_cpcr;
344 	u_char	res1[2];
345 	ushort	cp_rccr;
346 	u_char	res2;
347 	u_char	cp_rmds;
348 	u_char	res3[4];
349 	ushort	cp_cpmcr1;
350 	ushort	cp_cpmcr2;
351 	ushort	cp_cpmcr3;
352 	ushort	cp_cpmcr4;
353 	u_char	res4[2];
354 	ushort	cp_rter;
355 	u_char	res5[2];
356 	ushort	cp_rtmr;
357 	u_char	res6[0x14];
358 
359 	/* Baud rate generators.
360 	*/
361 	uint	cp_brgc1;
362 	uint	cp_brgc2;
363 	uint	cp_brgc3;
364 	uint	cp_brgc4;
365 
366 	/* Serial Communication Channels.
367 	*/
368 	scc_t	cp_scc[4];
369 
370 	/* Serial Management Channels.
371 	*/
372 	smc_t	cp_smc[2];
373 
374 	/* Serial Peripheral Interface.
375 	*/
376 	ushort	cp_spmode;
377 	u_char	res7[4];
378 	u_char	cp_spie;
379 	u_char	res8[3];
380 	u_char	cp_spim;
381 	u_char	res9[2];
382 	u_char	cp_spcom;
383 	u_char	res10[2];
384 
385 	/* Parallel Interface Port.
386 	*/
387 	u_char	res11[2];
388 	ushort	cp_pipc;
389 	u_char	res12[2];
390 	ushort	cp_ptpr;
391 	uint	cp_pbdir;
392 	uint	cp_pbpar;
393 	u_char	res13[2];
394 	ushort	cp_pbodr;
395 	uint	cp_pbdat;
396 
397 	/* Port E - MPC87x/88x only.
398 	 */
399 	uint	cp_pedir;
400 	uint	cp_pepar;
401 	uint	cp_peso;
402 	uint	cp_peodr;
403 	uint	cp_pedat;
404 
405 	/* Communications Processor Timing Register -
406 	   Contains RMII Timing for the FECs on MPC87x/88x only.
407 	*/
408 	uint	cp_cptr;
409 
410 	/* Serial Interface and Time Slot Assignment.
411 	*/
412 	uint	cp_simode;
413 	u_char	cp_sigmr;
414 	u_char	res15;
415 	u_char	cp_sistr;
416 	u_char	cp_sicmr;
417 	u_char	res16[4];
418 	uint	cp_sicr;
419 	uint	cp_sirp;
420 	u_char	res17[0xc];
421 
422 	u_char	res19[0x100];
423 	u_char	cp_siram[0x200];
424 
425 	/* The fast ethernet controller is not really part of the CPM,
426 	 * but it resides in the address space.
427 	 */
428 	fec_t	cp_fec;
429 	char	res18[0xE00];
430 
431 	/* The MPC885 family has a second FEC here */
432 	fec_t	cp_fec2;
433 #define cp_fec1	cp_fec	/* consistency macro */
434 
435 	/* Dual Ported RAM follows.
436 	 * There are many different formats for this memory area
437 	 * depending upon the devices used and options chosen.
438 	 * Some processors don't have all of it populated.
439 	 */
440 	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
441 
442 	/* Parameter RAM */
443 	union {
444 		u_char	cp_dparam[0x400];
445 		u16	cp_dparam16[0x200];
446 	};
447 } cpm8xx_t;
448 
449 /* Internal memory map.
450 */
451 typedef struct immap {
452 	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
453 	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
454 	memctl8xx_t	im_memctl;	/* Memory Controller */
455 	sit8xx_t	im_sit;		/* System integration timers */
456 	car8xx_t	im_clkrst;	/* Clocks and reset */
457 	sitk8xx_t	im_sitk;	/* Sys int timer keys */
458 	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
459 	char		res[96];
460 	i2c8xx_t	im_i2c;		/* I2C control/status */
461 	sdma8xx_t	im_sdma;	/* SDMA control/status */
462 	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
463 	iop8xx_t	im_ioport;	/* IO Port control/status */
464 	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
465 	cpm8xx_t	im_cpm;		/* Communication processor */
466 } immap_t;
467 
468 #endif /* __IMMAP_8XX__ */
469