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Searched refs:crc32ch (Results 1 – 25 of 68) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/crc/
Dinvalid.s45 crc32ch $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
46 crc32ch $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
47 crc32ch $1, $2, 2 # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
48 crc32ch $1, 2, $2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
49 crc32ch 1, $2, $2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
50 crc32ch $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
51 crc32ch $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
52 crc32ch $1, $2, 0($2) # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
Dvalid.s11 crc32ch $4, $5, $4 # CHECK: crc32ch $4, $5, $4 # encoding: [0x7c,0xa4,0x01,0x4f]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcrc32.ll36 ; CHECK: crc32ch r0, r0, r1
38 %val = call i32 @llvm.arm.crc32ch(i32 %cur, i32 %bits)
56 declare i32 @llvm.arm.crc32ch(i32, i32)
/external/llvm/test/CodeGen/ARM/
Dcrc32.ll36 ; CHECK: crc32ch r0, r0, r1
38 %val = call i32 @llvm.arm.crc32ch(i32 %cur, i32 %bits)
56 declare i32 @llvm.arm.crc32ch(i32, i32)
/external/llvm/test/MC/AArch64/
Dcyclone-crc.s17 crc32ch w3, w5, w7
23 CHECK: crc32ch w3, w5, w7
Darm64-basic-a64-instructions.s8 crc32ch w13, w17, w25
/external/llvm/test/CodeGen/AArch64/
Darm64-crc32.ll43 ; CHECK: crc32ch w0, w0, w1
45 %val = call i32 @llvm.aarch64.crc32ch(i32 %cur, i32 %bits)
69 declare i32 @llvm.aarch64.crc32ch(i32, i32)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-crc32.ll44 ; CHECK: crc32ch w0, w0, w1
46 %val = call i32 @llvm.aarch64.crc32ch(i32 %cur, i32 %bits)
70 declare i32 @llvm.aarch64.crc32ch(i32, i32)
/external/llvm/test/MC/ARM/
Dcrc32.s19 crc32ch r0, r1, r2
23 @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
Dcrc32-thumb.s19 crc32ch r0, r1, r2
23 @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
Ddirective-arch_extension-crc.s26 crc32ch r0, r1, r2
51 crc32ch r0, r1, r2
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dcrc32.s19 crc32ch r0, r1, r2
23 @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
Dcrc32-thumb.s19 crc32ch r0, r1, r2
23 @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
Ddirective-arch_extension-crc.s26 crc32ch r0, r1, r2
51 crc32ch r0, r1, r2
/external/capstone/suite/MC/ARM/
Dcrc32-thumb.s.cs6 0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2
Dcrc32.s.cs6 0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-basic-a64-instructions.s8 crc32ch w13, w17, w25
Dcrc.s34 crc32ch w3, w5, w7
/external/clang/test/CodeGen/
Darm64-crc32.c26 int crc32ch(int a, short b) in crc32ch() function
Darm-crc32.c25 int crc32ch(int a, short b) in crc32ch() function
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/crc/
Dvalid-32r6.txt8 0x7c 0xa4 0x01 0x4f # CHECK: crc32ch $4, $5, $4
Dvalid-32r6-el.txt8 0x4f 0x01 0xa4 0x7c # CHECK: crc32ch $4, $5, $4
/external/llvm/test/MC/Disassembler/ARM/
Dcrc32.txt7 # CHECK: crc32ch r0, r1, r2
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dcrc32-thumb.txt7 # CHECK: crc32ch r0, r1, r2
Dcrc32.txt7 # CHECK: crc32ch r0, r1, r2

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