| /external/llvm/test/MC/AArch64/ |
| D | directive-cpu.s | 25 crc32cx w0, w1, x3
29 crc32cx w0, w1, x3
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| D | cyclone-crc.s | 19 crc32cx w19, w23, x29
27 CHECK: crc32cx w19, w23, x29
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| D | arm64-basic-a64-instructions.s | 10 crc32cx w18, w16, xzr
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| D | basic-a64-instructions.s | 1506 crc32cx w18, w16, xzr
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-crc32.ll | 58 ; CHECK: crc32cx w0, w0, x1
59 %val = call i32 @llvm.aarch64.crc32cx(i32 %cur, i64 %next)
71 declare i32 @llvm.aarch64.crc32cx(i32, i64)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-crc32.ll | 59 ; CHECK: crc32cx w0, w0, x1
60 %val = call i32 @llvm.aarch64.crc32cx(i32 %cur, i64 %next)
72 declare i32 @llvm.aarch64.crc32cx(i32, i64)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-basic-a64-instructions.s | 10 crc32cx w18, w16, xzr
|
| D | crc.s | 36 crc32cx w19, w23, x29
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| D | directive-cpu.s | 16 crc32cx w0, w1, x3 label
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| D | directive-cpu-err.s | 24 crc32cx w0, w1, x3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-crc32.txt | 10 # CHECK: crc32cx w18, w16, xzr
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-crc32.txt | 10 # CHECK: crc32cx w18, w16, xzr
|
| D | basic-a64-instructions.txt | 1052 # CHECK: crc32cx w18, w16, xzr
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | crc32.ll | 58 declare i32 @llvm.arm.crc32cx(i32, i64)
|
| /external/llvm/test/CodeGen/ARM/ |
| D | crc32.ll | 58 declare i32 @llvm.arm.crc32cx(i32, i64)
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 726 TEST(crc32cx) { in TEST() argument
729 COMPARE(crc32cx(w7, w8, x9), "crc32cx w7, w8, x9"); in TEST()
730 COMPARE(crc32cx(w8, w19, x29), "crc32cx w8, w19, x29"); in TEST()
731 COMPARE(crc32cx(w18, w18, x4), "crc32cx w18, w18, x4"); in TEST()
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| D | test-cpu-features-aarch64.cc | 2775 TEST_CRC32(crc32cx_0, crc32cx(w0, w1, x2))
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 577 0x12,0x5e,0xdf,0x9a = crc32cx w18, w16, xzr
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 941 void crc32cx(const Register& wd, const Register& wn, const Register& xm);
|
| D | macro-assembler-aarch64.h | 3251 crc32cx(rd, rn, rm); in Crc32cx()
|
| D | assembler-aarch64.cc | 868 void Assembler::crc32cx(const Register& wd, in crc32cx() function in vixl::aarch64::Assembler
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 339 void crc32cx(const Register& wd, const Register& wn, const Register& xm)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 809 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1008 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 204 aarch64_crc32cx, // llvm.aarch64.crc32cx
|