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Searched refs:crs (Results 1 – 25 of 174) sorted by relevance

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/external/tensorflow/tensorflow/compiler/xla/service/
Dbfloat16_conversion_folding.cc38 Status HandleAllReduce(HloInstruction* crs) override;
179 Status BFloat16ConversionFoldingVisitor::HandleAllReduce(HloInstruction* crs) { in HandleAllReduce() argument
180 if (crs->IsCrossModuleAllReduce()) { in HandleAllReduce()
186 TF_RETURN_IF_ERROR(DefaultAction(crs)); in HandleAllReduce()
188 if (!bfloat16_support_->SupportsMixedPrecisions(*crs)) { in HandleAllReduce()
193 if (!crs->shape().IsTuple()) { in HandleAllReduce()
200 if (crs == computation_->root_instruction()) { in HandleAllReduce()
206 crs->operand_count()); in HandleAllReduce()
207 for (auto user : crs->users()) { in HandleAllReduce()
214 for (int64 i = 0; i < crs->operand_count(); ++i) { in HandleAllReduce()
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Dar_crs_combiner.h87 HloInstruction* crs; member
93 : ar(all_reduce), crs(cross_replica_sum), distance(dist) {} in ArCrsPair()
96 return absl::StrCat("(AR: ", ar->name(), ", CRS: ", crs->name(), in ToString()
Dbfloat16_conversion_folding_test.cc239 HloInstruction* crs = builder.AddInstruction(HloInstruction::CreateAllReduce( in TEST_F() local
244 HloInstruction::CreateGetTupleElement(f32_shape, crs, 0)); in TEST_F()
246 HloInstruction::CreateGetTupleElement(f32_shape, crs, 1)); in TEST_F()
261 EXPECT_EQ(crs->operand(0), a); in TEST_F()
262 EXPECT_EQ(crs->operand(1), b); in TEST_F()
265 EXPECT_EQ(ShapeUtil::GetSubshape(crs->shape(), {0}).element_type(), F32); in TEST_F()
266 EXPECT_EQ(ShapeUtil::GetSubshape(crs->shape(), {1}).element_type(), BF16); in TEST_F()
Dbfloat16_normalization_test.cc257 HloInstruction* crs = builder.AddInstruction(HloInstruction::CreateAllReduce( in TEST_F() local
262 HloInstruction::CreateGetTupleElement(bf16_shape, crs, 1)); in TEST_F()
270 EXPECT_EQ(crs->operand(1)->shape().element_type(), F32); in TEST_F()
271 EXPECT_EQ(ShapeUtil::GetSubshape(crs->shape(), {1}).element_type(), F32); in TEST_F()
Dar_crs_combiner.cc253 auto it = crs_reserved_map_.find(pair.crs); in GroupAllReducesById()
269 crs_reserved_map_[pair.crs] = ar_id; in GroupAllReducesById()
284 crs_reserved_map_[pair.crs] = ar_id; in GroupAllReducesById()
/external/llvm/test/tools/llvm-ar/
Ddefault-add.test5 RUN: llvm-ar crs %t.ar %t-macho.o
7 RUN: llvm-ar crs %t.ar %t-coff.o
11 RUN: llvm-ar crs %t.ar %t-coff.o
13 RUN: llvm-ar crs %t.ar %t-macho.o
Doverride.test4 RUN: llvm-ar -format gnu crs %t.ar %t.o
Ddefault-macho.test4 RUN: llvm-ar crs %t.ar %t.o
Ddefault-elf.test4 RUN: llvm-ar crs %t.ar %t.o
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-ar/
Ddefault-add.test5 RUN: llvm-ar crs %t.ar %t-macho.o
8 RUN: llvm-ar -crs %t.ar %t-coff.o
12 RUN: llvm-ar crs %t.ar %t-coff.o
14 RUN: llvm-ar crs %t.ar %t-macho.o
Dregex-cmd.test4 RUN: llvm-ar crs %t.ar %t.*
Doverride.test4 RUN: llvm-ar -format gnu crs %t.ar %t.o
Ddefault-macho.test4 RUN: llvm-ar crs %t.ar %t.o
Ddefault-elf.test4 RUN: llvm-ar crs %t.ar %t.o
/external/openssh/
Dkrl.c244 struct revoked_serial rs, *ers, *crs, *irs; in insert_serial_range() local
283 while ((crs = RB_PREV(revoked_serial_tree, rt, ers)) != NULL) { in insert_serial_range()
284 KRL_DBG(("%s: pred %llu:%llu", __func__, crs->lo, crs->hi)); in insert_serial_range()
285 if (ers->lo != 0 && crs->hi < ers->lo - 1) in insert_serial_range()
288 if (crs->lo < ers->lo) { in insert_serial_range()
289 ers->lo = crs->lo; in insert_serial_range()
293 RB_REMOVE(revoked_serial_tree, rt, crs); in insert_serial_range()
294 free(crs); in insert_serial_range()
297 while ((crs = RB_NEXT(revoked_serial_tree, rt, ers)) != NULL) { in insert_serial_range()
298 KRL_DBG(("%s: succ %llu:%llu", __func__, crs->lo, crs->hi)); in insert_serial_range()
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/external/python/cpython2/PC/os2emx/
DMakefile82 ARFLAGS= crs
124 ARFLAGS= -p64 crs
126 ARFLAGS= -p32 crs
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-strings/
Dnested-archives.test2 RUN: llvm-ar -format gnu crs %t/inner.a %S/Inputs/abcd
3 RUN: llvm-ar -format gnu crs %t/outer.a %t/inner.a
Darchive-filename.test2 RUN: llvm-ar -format gnu crs %t/archive.a %S/Inputs/abcd
/external/syzkaller/pkg/ifuzz/
Dencode.go183 crs := []byte{0, 2, 3, 4}
184 reg = crs[r.Intn(len(crs))]
/external/iptables/extensions/
DGNUmakefile.in130 ${AM_VERBOSE_AR} ${AR} crs $@ $^;
133 ${AM_VERBOSE_AR} ${AR} crs $@ $^;
136 ${AM_VERBOSE_AR} ${AR} crs $@ $^;
139 ${AM_VERBOSE_AR} ${AR} crs $@ $^;
142 ${AM_VERBOSE_AR} ${AR} crs $@ $^;
/external/tensorflow/tensorflow/compiler/xla/service/gpu/
Dir_emitter_unnested.cc1389 Status IrEmitterUnnested::HandleAllReduce(HloInstruction* crs) { in HandleAllReduce() argument
1391 << "; operand count: " << crs->operand_count() in HandleAllReduce()
1398 crs->IsCrossReplicaAllReduce() && in HandleAllReduce()
1399 crs->operand_count() == 1 && // One array to reduce. in HandleAllReduce()
1400 crs->operand(0)->shape().element_type() == F32 && in HandleAllReduce()
1402 IsScalarAddComputation(crs->to_apply()); in HandleAllReduce()
1405 CHECK(crs->operand(0)->shape().IsArray()) in HandleAllReduce()
1406 << "Operands to all-reduce must be arrays: " << crs->ToString(); in HandleAllReduce()
1409 /*elements=*/ShapeUtil::ElementsIn(crs->operand(0)->shape()), in HandleAllReduce()
1410 /*source_address=*/GetAllocationSlice(*crs->operand(0)), in HandleAllReduce()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-objcopy/
Dstrip-debug.test25 # RUN: llvm-ar crs %t.a %t
34 # RUN: llvm-ar crs %t.multiple-stripped-obj.a %t2 %t.duplicate.stripped
36 # RUN: llvm-ar crs %t.multiple-obj.a %t %t.duplicate
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dldr-str-imm12.ll23 …union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need…
56 …union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need…
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dldr-str-imm12.ll23 …union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need…
56 …union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need…
/external/llvm/test/CodeGen/Thumb2/
Dldr-str-imm12.ll23 …union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need…
56 …union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need…

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