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Searched refs:cs_ena (Results 1 – 13 of 13) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_spd.c581 u32 cs, cl, cs_num, cs_ena; local
653 cs_ena = 0;
655 cs_ena = ddr3_get_cs_ena_from_reg();
663 !(cs_ena & (1 << cs))) {
665 cs_ena |= (0x1 << cs);
667 cs_ena |= (0x3 << cs);
669 cs_ena |= (0x7 << cs);
671 cs_ena |= (0xF << cs);
681 if (cs_ena > 0xF) {
897 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
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Dddr3_write_leveling.c86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
229 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
431 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
509 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw_reg_dimm()
530 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
619 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
679 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
682 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
722 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
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Dddr3_hw_training.c94 dram_info.cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_hw_training()
228 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
319 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
455 dram_info.cs_ena = 1; in ddr3_hw_training()
665 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
713 tmp_cs = dram_info->cs_ena; in ddr3_save_training()
891 dram_info->cs_ena = 0x1; in ddr3_check_if_resume_mode()
900 dram_info->cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_check_if_resume_mode()
956 dram_info->cs_ena = 1; in ddr3_training_suspend_resume()
1089 u32 cs_ena, reg; in ddr3_odt_read_dynamic_config() local
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Dddr3_init.c142 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
169 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
185 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
198 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_save_and_set_training_windows() local
232 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
1072 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_get_cs_num_from_reg() local
1077 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
Dddr3_dfs.c196 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
442 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
468 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
676 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
1005 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1009 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_dfs_low_2_high()
1137 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_low_2_high()
1163 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1436 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
Dddr3_dqs.c151 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
233 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_tx()
334 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_find_adll_limits()
1335 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_dqs_patterns()
1338 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_dqs_patterns()
Dddr3_read_leveling.c74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
196 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
Dxor.c51 if (dram_info->cs_ena & (1 << ui)) { in mv_sys_xor_init()
Dddr3_hw_training.h253 u32 cs_ena; member
Dddr3_pbs.c1560 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_pbs_patterns()
1563 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_pbs_patterns()
/external/u-boot/drivers/ddr/marvell/a38x/
Dxor.c20 void mv_sys_xor_init(u32 num_of_cs, u32 cs_ena, uint64_t cs_size, u32 base_delta) in mv_sys_xor_init() argument
37 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
51 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
341 u32 cs_ena = 0; in ddr3_new_tip_ecc_scrub() local
348 cs_ena |= 1 << cs_c; in ddr3_new_tip_ecc_scrub()
353 mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); in ddr3_new_tip_ecc_scrub()
Dmv_ddr_plat.c1024 static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) in ddr3_fast_path_dynamic_cs_size_config() argument
1039 if (cs_ena & (1 << cs)) { in ddr3_fast_path_dynamic_cs_size_config()
1108 u32 cs_ena = mv_ddr_sys_env_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
1122 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
1128 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
1142 u32 cs_ena; in ddr3_save_and_set_training_windows() local
1161 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
1175 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
Dddr3_init.h185 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);