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Searched refs:cs_enable_reg_val (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_centralization.c72 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_centralization() local
84 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
483 cs_enable_reg_val[if_id], in ddr3_tip_centralization()
505 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_special_rx() local
521 cs_enable_reg_val, in ddr3_tip_special_rx()
Dddr3_training_leveling.c68 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_read_leveling() local
90 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, in ddr3_tip_dynamic_read_leveling()
320 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
432 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; /* save current CS value */ in ddr3_tip_dynamic_per_bit_read_leveling() local
465 DUAL_DUNIT_CFG_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
773 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
834 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_write_leveling() local
867 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_dynamic_write_leveling()
1169 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
Dddr3_training_pbs.c48 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_pbs() local
61 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
868 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_pbs()