Home
last modified time | relevance | path

Searched refs:csinv (Results 1 – 25 of 41) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dcond-sel.ll107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt
160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
Dcond-sel-value-prop.ll67 ; CHECK: csinv x0, x[[REG]], xzr, ne
94 ; CHECK: csinv x0, x[[REG]], xzr, eq
105 ; CHECK: csinv w0, w[[REG]], wzr, eq
Darm64-early-ifcvt.ll114 ; CHECK-NEXT: csinv w0, w1, w0, eq
132 ; CHECK-NEXT: csinv x0, x1, x0, eq
150 ; CHECK-NEXT: csinv w0, w1, w0, ne
168 ; CHECK-NEXT: csinv x0, x1, x0, ne
Dwin64_vararg.ll130 ; CHECK: csinv w0, w0, wzr, ge
237 ; CHECK: csinv w0, w0, wzr, ge
Darm64-csel.ll105 ; CHECK: csinv w0, w1, w2, ne
/external/llvm/test/CodeGen/AArch64/
Dcond-sel.ll107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt
160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
Dfp16-v4-instructions.ll303 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc
304 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc
305 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc
306 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc
421 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le
422 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le
423 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le
424 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le
Darm64-early-ifcvt.ll114 ; CHECK-NEXT: csinv w0, w1, w0, eq
132 ; CHECK-NEXT: csinv x0, x1, x0, eq
150 ; CHECK-NEXT: csinv w0, w1, w0, ne
168 ; CHECK-NEXT: csinv x0, x1, x0, ne
Darm64-csel.ll104 ; CHECK: csinv w0, w1, w2, ne
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs516 0x01,0x10,0x93,0x5a = csinv w1, w0, w19, ne
517 0xbf,0x00,0x89,0x5a = csinv wzr, w5, w9, eq
518 0xe9,0xc3,0x9e,0x5a = csinv w9, wzr, w30, gt
519 0x81,0x43,0x9f,0x5a = csinv w1, w28, wzr, mi
520 0xf3,0xb2,0x9d,0xda = csinv x19, x23, x29, lt
521 0x7f,0xa0,0x84,0xda = csinv xzr, x3, x4, ge
522 0xe5,0x23,0x86,0xda = csinv x5, xzr, x6, hs
523 0x07,0x31,0x9f,0xda = csinv x7, x8, xzr, lo
534 0xf4,0x03,0x9f,0x5a = csinv w20, wzr, wzr, eq
535 0xfe,0xb3,0x9f,0xda = csinv x30, xzr, xzr, lt
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1365 csinv w1, w0, w19, ne
1366 csinv wzr, w5, w9, eq
1367 csinv w9, wzr, w30, gt
1368 csinv w1, w28, wzr, mi
1374 csinv x19, x23, x29, lt
1375 csinv xzr, x3, x4, ge
1376 csinv x5, xzr, x6, cs
1377 csinv x7, x8, xzr, cc
Darm64-arithmetic-encoding.s554 csinv w1, w2, w3, eq
555 csinv x1, x2, x3, eq
Dbasic-a64-diagnostics.s1371 csinv w20, wsp, wsp, mi
1372 csinv sp, x30, x29, le
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1365 csinv w1, w0, w19, ne
1366 csinv wzr, w5, w9, eq
1367 csinv w9, wzr, w30, gt
1368 csinv w1, w28, wzr, mi
1374 csinv x19, x23, x29, lt
1375 csinv xzr, x3, x4, ge
1376 csinv x5, xzr, x6, cs
1377 csinv x7, x8, xzr, cc
Darm64-arithmetic-encoding.s554 csinv w1, w2, w3, eq
555 csinv x1, x2, x3, eq
Dbasic-a64-diagnostics.s1366 csinv w20, wsp, wsp, mi
1367 csinv sp, x30, x29, le
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-arithmetic.txt520 # CHECK: csinv w1, w2, w3, eq
522 # CHECK: csinv x1, x2, x3, eq
Dbasic-a64-instructions.txt912 # CHECK: csinv w1, w0, w19, ne
913 # CHECK: csinv wzr, w5, w9, eq
914 # CHECK: csinv w9, wzr, w30, gt
915 # CHECK: csinv w1, w28, wzr, mi
916 # CHECK: csinv x19, x23, x29, lt
917 # CHECK: csinv xzr, x3, x4, ge
918 # CHECK: csinv x5, xzr, x6, hs
919 # CHECK: csinv x7, x8, xzr, lo
952 # CHECK: csinv x3, xzr, xzr, nv
985 # CHECK: csinv x1, x0, x0, al
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-arithmetic.txt520 # CHECK: csinv w1, w2, w3, eq
522 # CHECK: csinv x1, x2, x3, eq
Dbasic-a64-instructions.txt911 # CHECK: csinv w1, w0, w19, ne
912 # CHECK: csinv wzr, w5, w9, eq
913 # CHECK: csinv w9, wzr, w30, gt
914 # CHECK: csinv w1, w28, wzr, mi
915 # CHECK: csinv x19, x23, x29, lt
916 # CHECK: csinv xzr, x3, x4, ge
917 # CHECK: csinv x5, xzr, x6, hs
918 # CHECK: csinv x7, x8, xzr, lo
951 # CHECK: csinv x3, xzr, xzr, nv
984 # CHECK: csinv x1, x0, x0, al
[all …]
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h443 csinv(rd, rn, rm, cond); in Csinv()
Dassembler-arm64.cc1362 void Assembler::csinv(const Register& rd, in csinv() function in v8::internal::Assembler
1388 csinv(rd, zr, zr, NegateCondition(cond)); in csetm()
1400 csinv(rd, rn, rn, NegateCondition(cond)); in cinv()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour78 0x~~~~~~~~~~~~~~~~ 5a83005d csinv w29, w2, w3, eq
79 0x~~~~~~~~~~~~~~~~ 5a83105d csinv w29, w2, w3, ne
80 0x~~~~~~~~~~~~~~~~ da8630a4 csinv x4, x5, x6, lo
81 0x~~~~~~~~~~~~~~~~ da8620a4 csinv x4, x5, x6, hs
Dlog-disasm78 0x~~~~~~~~~~~~~~~~ 5a83005d csinv w29, w2, w3, eq
79 0x~~~~~~~~~~~~~~~~ 5a83105d csinv w29, w2, w3, ne
80 0x~~~~~~~~~~~~~~~~ da8630a4 csinv x4, x5, x6, lo
81 0x~~~~~~~~~~~~~~~~ da8620a4 csinv x4, x5, x6, hs
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc131 __ csinv(w29, w2, w3, eq); in GenerateTestSequenceBase() local
132 __ csinv(w29, w2, w3, ne); in GenerateTestSequenceBase() local
133 __ csinv(x4, x5, x6, cc); in GenerateTestSequenceBase() local
134 __ csinv(x4, x5, x6, cs); in GenerateTestSequenceBase() local

12