Searched refs:ctl_reg (Results 1 – 4 of 4) sorted by relevance
43 u32 *cfg_reg, *ctl_reg; in mx3_setup_sdram_bank() local50 ctl_reg = &esdc->esdctl0; in mx3_setup_sdram_bank()54 ctl_reg = &esdc->esdctl1; in mx3_setup_sdram_bank()83 ctl_reg); in mx3_setup_sdram_bank()88 ctl_reg); in mx3_setup_sdram_bank()96 ctl_reg); in mx3_setup_sdram_bank()101 ctl_reg); in mx3_setup_sdram_bank()106 ctl_reg); in mx3_setup_sdram_bank()115 ctl_reg); in mx3_setup_sdram_bank()
247 u32 ctl_reg; in dnet_phy_init() local300 ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG); in dnet_phy_init()303 ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); in dnet_phy_init()305 ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; in dnet_phy_init()307 dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); in dnet_phy_init()
31 unsigned char ctl_reg; member
62 port[num].ctl_reg = 0x08; /*Default value of control reg */ in sata_bus_softreset()63 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()65 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()67 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()