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Searched refs:ctrl_adll1 (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c90 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM]; variable
1492 ctrl_adll1[adll] = 0; in ddr3_tip_run_leveling_sweep_test()
1500 ddr3_tip_read_adll_value(dev_num, ctrl_adll1, in ddr3_tip_run_leveling_sweep_test()
1523 gap = ctrl_adll1[if_id * cs * octets_per_if_num + pup] - in ddr3_tip_run_leveling_sweep_test()
1597 ctrl_adll1[if_id * in ddr3_tip_run_leveling_sweep_test()
1634 ddr3_tip_write_adll_value(dev_num, ctrl_adll1, CTX_PHY_REG(cs)); in ddr3_tip_run_leveling_sweep_test()