Home
last modified time | relevance | path

Searched refs:ctrl_core_sma_sw_0 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-omap2/omap5/
Ddra7xx_iodelay.c35 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
38 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
Dprcm-regs.c385 .ctrl_core_sma_sw_0 = 0x4A0023FC,
1021 (*ctrl)->ctrl_core_sma_sw_0; in clrset_spare_register()
/external/u-boot/arch/arm/include/asm/
Domap_common.h482 u32 ctrl_core_sma_sw_0; member